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Tables
Table 2-1. PPC405GP PLB Agents as Masters and Slaves ............................................................................. 2-2
Table 2-2. Registers Controlling PLB Master Priority Assignments .................................................................. 2-3
Table 2-3. P,LB Arbiter Registers ...................................................................................................................... 2-5
Table 2-4. PLB Arbiter Registers ...................................................................................................................... 2-8
Table 2-5. PPC405GP OPB Master Assignments .......................................................................................... 2-12
Table 2-6. PLB Arbiter Registers .................................................................................................................... 2-12
Table 3-1. PPC405GP Address Space ............................................................................................................. 3-2
Table 3-2. PPC405GP SPRs ........................................................................................................................... 3-7
Table 3-3. XER[CA] Updating Instructions ..................................................................................................... 3-10
Table 3-4. XER[SO,OV] Updating Instructions .............................................................................................. 3-11
Table 3-5. Time Base Registers ..................................................................................................................... 3-15
Table 3-6. Directly Accessed DCRs ............................................................................................................... 3-17
Table 3-7. SDRAM Controller DCR Usage .................................................................................................... 3-19
Table 3-8. Offsets for SDRAM Controller Registers ...................................................................................... 3-19
Table 3-9. External Bus Controller DCR Usage ............................................................................................. 3-20
Table 3-10. Offsets for External Bus Controller Registers ............................................................................. 3-20
Table 3-11. Decompression Controller DCR Usage ...................................................................................... 3-21
Table 3-12. Offsets for Decompression Controller Registers ......... ~ .............................................................. 3-21
Table 3-13. Directly Accessed MMIO Registers ............................................................................................ 3-22
Table 3-14. PCI Configuration Address and Data Registers ......................................................................... 3-25
Table 3-15. PCI Configuration Registers ...................................................................................................... 3-25
Table 3-16. Alignment Exception Summary ................................................................................................... 3-28
Table 3-17. Bits of the BO Field ..................................................................................................................... 3-35
Table 3-18. Conditional Branch BO Field ...................................................................................................... 3-36
Table 3-19. Example Memory Mapping .......................................................................................................... 3-40
Table 3-20. Privileged Instructions ................................................................................................................. 3-42
Table 3-21. PPC405GP Instruction Set Summary .......................................................................................... 3-47
Table 3-22. Implementation-specific Instructions ............................................................................................ 3-48
Table 3-23. Storage Reference Instructions .................................................................................................. 3-48
Table 3-24. Arithmetic Instructions ................................................................................................................ 3-49
Table 3-25. Multiply-Accumulate and Multiply Halfword Instructions .............................................................. 3-50
Table 3-26. Logical Instructions ..................................................................................................................... 3-50
Table 3-27. Compare Instructions .................................................................................................................. 3-50
Table 3-28. Branch Instructions ..................................................................................................................... 3-51
Table 3-29. CR Logical Instructions ............................................................................................................... 3-51
Table 3-30. Rotate Instructions ...................................................................................................................... 3-51
Table 3-31. Shift Instructions ......................................................................................................................... 3-52
Table 3-32. Cache Management Instructions ................................................................................................ 3-52
Table 3-33. Interrupt Control Instructions ...................................................................................................... 3-52
Table 3-34., TLB Management Instructions .................................................................................................... 3-53
Table 3-35. Processor Management Instructions .......................................................................................... 3-53
Table 4-1. Instruction Cache Organization ....................................................................................................... 4-2
Preliminary
Tables
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