Table of Contents
Advertisement
Figure 19-38 illustrates the different phases in the EMAC-MAL communication.
Frame
/.
\
/.
Packet
Status
Idle:
Packet
phase
phase
: phase:
phase
r
~
~
r
Command
Data
Status
write
transfer
read
Figure 19-38. EMAC-MAL Communication Phases
During the packet and status phases EMAC signals a request for service by driving its arbitration level
signal to a non-idle level.
19.10 Programming Notes
Certain combinations in device drivers are not allowed when writing to EMAC registers. When
creating device drivers, ensure that the following guidelines are used:
• In dependent mode, EMACO_MR1[TRO] must be equal EMACO_MR1[TR1]
• When internalloopback is enabled (EMACO_MR1 [ILE] = 1), EMAC must be configured in full-
duplex mode (EMACO_MR1 [FDE] =1)
• EMACO_MR1 [1ST] =0 only"when EMACO_MR1 [MF] = 1
°
and EMACO_MR1 [FDE] =0
• In dependent mode, EMACO_ISER
24 ,25
must equal EMACO_ISER
27 ,28
• EMACO_MR1[EIFC] =0 if EMACO_MR1[FDE] =0
• EMACO_ TMR1 [TLR] must be greater than the MAL burst size in entities (6 for MAL)
• EMACO_ TMR1 [TUR] must be greater or equal to EMACO_ TMR1 [TLR] and less than the Transmit
FIFO size in entries (EMACO_MR1 [TFS])
• To avoid deadlock, the sum of EMACO_ TMR1 [TLR] and the EMACO_ TRTR[TRT] must be at least
four less than the Transmit FIFO size specified in EMACO_MR1 [TFS]
• EMACO_RWMR[RLWM] must be greater than the MAL burst size in entities (six for MAL)
• EMACO_RWMR[RHWM] must be greater than EMACO_RWMR[RLWM]
• EMACO_RWMR[RHWM] must be less than the Receive FIFO size in entities (EMACO_MR1 [RFS])
19.10.1 Power-Up and Initialization
19.10.1.1 Reset Options
The EMAC must be reset before performing configuration changes. The following types of reset
operations can be applied to EMAC.
19-44
PPC405GP User's Manual
Preliminary
Advertisement
Chapters
Table of Contents
