Dcu Debugging - IBM PowerPC 405GP User Manual

Embedded processor
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ICU tag information is placed into the ICDBDR as shown:
0:21
TAG
Cache Tag
22:26
Reserved
27
V
Cache Line Valid
o
Not valid
1 Valid
28:30
Reserved
31
LRU
Least Recently Used (LRU)
o
A-way LRU
1 B-way LRU
If CCRO[CIS]
=
0, the data is a word of ICU data from the addressed line, specified by EA
27 : 29 .
If
CCRO[CWS]
=
0, the data is from the A-way; otherwise; the data from the B-way.
If CCRO[CIS]
=
1, the cache information is the cache tag. If CCRO[CWS]
=
0, the tag is from the A-
way; otherwise, the tag is from the B-way.
Programming Note: The instruction pipeline does not wait for data from an icread instruction to
arrive before attempting to use the contents the ICDBDR. The following code sequence ensures
proper results:
icread r5,r6# read cache information
isync
# ensure completion of icread
mficdbdr r7# move information to GPR
4.4.3
DCU Debugging
The dcread instruction provides a debugging tool for reading the data cache entries for the
congruence class specified by EA
20 : 26 .
The cache information is read into a GPR.
If CCRO[CIS]
=
0, the data is a word of DCU data from the addressed line, specified by EA
27 : 29 .
If
CCRO[CWS]
=
0, the data is from the A-way; otherwise; the data is from the B-way.
If CCRO[CIS]
=
1, the cache information is the cache tag. If CCRO[CWS]
=
0, the tag is from the A-
way; otherwise the tag is from the B-way.
Preliminary
Cache Operations
4-15

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