Device-Paced Transfers - IBM PowerPC 405GP User Manual

16.4 Device-Paced Transfers
For device-paced transfers, the EBC provides two distinct modes: Sample On Ready enabled and
Sample On Ready disabled. The selection of these modes is controlled on a per-bank basis by
EBCO_BnAP[SOR]. When Sample On Ready is enabled (EBCO_BnAP[SOR] = 1) data is transferred
on the PerClk rising edge where PerReady is sampled active. When Sampling On Ready is disabled
(EBCO_BnAP[SOR] = 0), PerReady sampled active causes the data transfer to occur in the next
cycle, which results in an additional cycle of wait time.
The ready signal (PerReady) is an input which allows the insertion of externally generated (device-
paced) wait states. PerReady is monitored only when EBCO_BnAP[RE]=1 .
• For burst disabled banks (EBCO_BnAP[BME] = 0) sampling of the PerReady input starts
EBCO_BnAP[TWT] cycles after the beginning of the transfer. Wait states are inserted and sampling
continues once per cycle until either PerReady is high when sampled or a timeout occurs.
• For burst enabled banks (EBCO_BnAP[BME] = 1) sampling of the PerReady input starts
EBCO_BnAP[FWT] PerClk cycles after the beginning of the first transfer of a burst, and
EBCO_BnAP[BWT] cycles after the beginning of subsequent transfers of the burst. Sampling
continues once per cycle until either PerReady is sampled high or a timeout occurs.
• When EBCO_BnAP[SOR] = 1 data transfer occurs in the same cycle where PerReady is sampled
active. In contrast, if EBCO_BnAP[SOR]=O the data transfer occurs in the next cycle.
• When EBCO_BnAP[SOR] = 1, if the hold time is set to zero, EBCO_BnAP[TH] = 0, the programmed
hold time is ignored and the EBC performs the transaction with one hold cycle.
• When EBCO_BnAP[RE] = 1, the Write Byte Enable Off parameter must be programmed to zero,
EBCO_BnAP[WBF] = 0.
The EBC may be programmed to wait only a limited time for PerReady to become active, or it may be
programmed for unlimited wait. If EBCO_CFG[PTD] = 1, timeouts are disabled and the EBC waits
indefinitely for an active PerReady.
If EBCO_CFG[PTD] = 0, device-paced timeouts are enabled and the EBC only waits for the number of
PerClk cycles programmed in EBCO_CFG[RTC]. The timeout counter is reset whenever the
peripheral address changes. In this manner each data element within a device-paced burst
transaction is treated separately for the purposes of determining whether a timeout error occurs.
If
PerReady does not become active before the timeout counter reaches the value programmed into
EBCO_CFG[RTC], the transfer is aborted and an error is signalled. See "Error Reporting" on
page 16-29 for details on how timeout errors are logged.
External Bus Controller 16-11