Instruction Processing; Figure 3-13. Byte-Reverse Word Load Or Store (Big Endian Storage Region); Figure 3-14. Normal Word Load Or Store (Little Endian Storage Region) - IBM PowerPC 405GP User Manual

Figure 3-13 illustrates the contents of a GPR and memory (starting at address 00) after a load/store
with byte-reverse in a big endian storage region.
MSB
11
14
OxOO
12
13
Ox01
13
12
Ox02
LSB
14
11
Ox03
GPR
Memory
Figure 3-13. Byte-Reverse Word, Load or Store (Big Endian Storage Region)
Note that the results are identical to the results of a normal load/store in a little end ian storage region,
as illustrated in Figure 3-14.
MSB
11
14
OxOO
I
12
13
Ox01
13
12
Ox02
LSB
14
11
Ox03
GPR
Memory
Figure 3-14. Normal Word Load or Store (Little Endian Storage Region)
The E storage attribute augments the byte-reverse load/store instructions in two important ways:
• The load/store with byte-reverse instructions do not solve the problem of fetching instructions from
a storage region in little endian format.
Only the end ian storage attribute mechanism supports the fetching of little end ian program images.
• Typical compilers cannot make general use of the byte-reverse load/store instructions, so these
instructions are ordinarily used only in device drivers written in hand-coded assembler.
Compilers can, however, take full advantage of the endian storage attribute mechanism, enabling
application programmers working in a high-level language, such as C, to compile programs and
data structures into little end ian format.
3.6 Instruction Processing
The instruction pipeline, illustrated in Figure 3-15, contains three queue locations: prefetch buffer 1
(PFB1), prefetch buffer 0 (PFBO), and decode (DCD). This queue implements a pipeline with the
following functional stages: fetch, decode, execute, write-back and load write-back. Instructions are
fetched from the instruction cache unit (ICU), placed in the instruction queue, and eventually
dispatched to the execution unit (EXU).
Instructions are fetched from the ICU at the request of the EXU. Cachable instructions are forwarded
directly to the instruction queue and stored in the ICU cache array. Non-cachable instructions are also
forwarded directly to the instruction queue, but are not stored in the ICU cache array. Fetched
Preliminary Programming Model
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