Pid Indirect Access Registers; I/O Window Register Format; X)Apic Eoi Register Format - Intel 460GX Software Developer’s Manual

Register Descriptions
2.6.2.2 I/O Window Register (FEC00010h)
This register is mapped onto the PID's internal register that is selected by the I/O register select
register. Readability/writeability by software is determined by the characteristics of the internal
register that is currently selected. The format of the I/O window register is shown in
below. This register must be accessed using 32-bit read or write operations.
Table 2-4. I/O Window Register Format
Register Offset: FEC00010hDefault Value: [00000000h]Attribute: Read/Write
Bit(s)
31:0
2.6.2.3 (x)APIC EOI Register (FEC00040h)
The (x)APIC EOI register provides a means of informing the PID that interrupt service has been
completed by the processor for a given interrupt vector (mapped to 1 of 64 interrupt inputs received
by the PID). The PID will compare this vector value with the vector field of each entry in the RT.
When a match is found, the RIRR bit for that entry will be cleared. In the case of level-triggered
interrupts, clearing the remote IRR bit will initiate a resampling of the corresponding interrupt
input signal. If the interrupt input is still asserted, the PID will issue a new level-triggered interrupt
message. The PID will therefore issue a single new interrupt message upon receiving an EOI write,
corresponding to the still asserted interrupt input pin. The PID only uses the (x)APIC EOI register
in SAPIC mode.
Note: If multiple redirection entries assign the same vector for more than one interrupt pin, each of those
pins will be resampled and new interrupt messages issued for those that are still asserted. This
register must be accessed using 32-bit read or write operations.
Table 2-5. (x)APIC EOI Register Format
Register Offset: FEC00040hDefault Value: [00000000h]Attribute: Read/Write
Bit(s)
31:8
7:0
2.6.3

PID Indirect Access Registers

The PID provides several indirect access registers. These registers are accessed via the I/O select
and I/O window registers described above. The indirect access registers include the (x)APIC ID,
version, and arbitration ID registers, and 64 RTEs for each of the 64 interrupt inputs to the PID.
Registers at offsets 03h-0Fh are reserved and will return a 00h value when read.
Table 2-6
2-46
Name
IOWIN[31:0] This 32-bit register contains the 32-bit write or read data value.
Name
Reserved Reserved
SAPICEOI[7:0] Interrupt vector
summarizes the indirect access registers. Detailed descriptions of each register follow.
Description
Description
Intel® 460GX Chipset Software Developer's Manual
Table 2-4