Memory Subsystem; Organization; General Memory Characteristics - Intel 460GX Software Developer’s Manual

Memory Subsystem

The Intel 460GX chipset's memory subsystem consists of the SAC's DRAM controller, the SDC's
buffering and datapath access, the MAC and MDC components, and the DRAMs themselves.
Table 5-1
Table 5-1. General Memory Characteristics
DRAM Types
Maximum Memory Size
Minimum Memory
Memory Increment
Memory Modules
DRAM Sizes
DIMMs/Row
Rows/Stack
Stacks/Card
Cards/System
DRAM Types
The SAC's DRAM controller provides addresses and commands to the 2 MAC's on each memory
card. The MAC generates row and column addresses for the DRAM array and controls the data
flow through the MDC. For processor-memory cycles, the address is received from the system bus,
and data flows through the SDC to/from the memory cards. For PCI-DRAM cycles, the address is
presented on the bus. The data moves between PCI and DRAM within the SAC/SDC, without
appearing on the system bus. AGP-DRAM cycles are done non-coherently (unless coherent AGP is
being used) and therefore do not have their addresses placed on the bus. The data for AGP
transactions, like PCI cycles, flows to/from the DRAM within the SAC/SDC.
5.1

Organization

The 460GX chipset supports 1 or 2 memory cards. Each card supports up to 8 GB of memory using
128 MB DIMM's (32 GB with 1 GB DIMM's); 2 cards provide up to 16 GB of memory (64 GB
with 1 GB DIMM's). There are 2 independent interfaces to the SAC/SDC from the memory
subsystem, running simultaneously. Each memory interface supports 1 card and has a 72-bit
datapath and a separate control path. Running at 266 MHz, each interface allows a 2.13 GB/s peak
transfer rate, for a total of 4.27 GB/s of Bandwidth.
configuration. platform.
Intel® 460GX Chipset Software Developer's Manual
summarizes the 460GX chipset's general memory characteristics.
Synchronous DRAM (SDRAM)
Up to 4 GB using 16MB DIMM's, up to 16 GB using 128 MB DIMM's, or 64 GB
using 1 GB DIMM's
64 MB using 16MB DIMM's, 256 MB using 1 GB DIMM's
64 MB is the smallest increment
168 pin (x72) 3.3 volt DIMMs
16 Mbit, 64 Mbit, 128Mbit, 256 Mbit
4 DIMMs per row which must be populated as a unit
Up to 4 rows per stack; may populate any number of rows
2 stacks per card; may populate either 1 or 2 stacks
2 cards per system; 1 card per memory port, may have either one or two cards
in the system
Synchronous DRAM (SDRAM)
Figure 5-1 illustrates this maximum
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5-1