Intel SL8J6 - Pentium 4 Processor Datasheet
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Intel SL8J6 - Pentium 4 Processor Datasheet

Pentium 4 processor on 90 nm process
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®
®
Intel
Pentium
4 Processor on
90 nm Process
Datasheet
2.80 GHz – 3.40 GHz Frequencies Supporting Hyper-Threading
1
Technology
for All Frequencies with 800 MHz Front Side Bus
February 2005
Document Number: 300561-003

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Summary of Contents for Intel SL8J6 - Pentium 4 Processor

  • Page 1 ® ® Intel Pentium 4 Processor on 90 nm Process Datasheet 2.80 GHz – 3.40 GHz Frequencies Supporting Hyper-Threading Technology for All Frequencies with 800 MHz Front Side Bus February 2005 Document Number: 300561-003...
  • Page 2 HT Technology. Intel, Pentium, Intel NetBurst, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.

  • Page 3: Table Of Contents

    Contents Introduction ........................9 Terminology......................10 1.1.1 Processor Packaging Terminology............10 References ......................11 Electrical Specifications ..................13 Power and Ground Pins ..................13 Decoupling Guidelines ..................13 2.2.1 Decoupling ..................13 2.2.2 FSB GTL+ Decoupling ................13 2.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking........14 Voltage Identification ...................
  • Page 4 5.2.2 On-Demand Mode.................. 68 5.2.3 PROCHOT# Signal Pin ................68 5.2.4 THERMTRIP# Signal Pin ............... 69 5.2.5 and Fan Speed Reduction............69 control 5.2.6 Thermal Diode..................69 Features ........................71 Power-On Configuration Options ................ 71 Clock Control and Low Power States..............72 6.2.1 Normal State—State 1 ................
  • Page 5 Figures Phase Lock Loop (PLL) Filter Requirements ............16 Static and Transient Tolerance for Loadline A..........24 Static and Transient Tolerance for Loadline B..........26 Overshoot Example Waveform..............30 Processor Package Assembly................31 Processor Package Drawing (Sheet 1 of 2) ............33 Processor Package Drawing (Sheet 2 of 2) ............
  • Page 6 Tables References......................11 Core Frequency to FSB Multiplier Configuration..........14 Voltage Identification Definition................15 FSB Pin Groups ....................18 Signal Characteristics ..................19 Signal Reference Voltages.................. 19 BSEL[1:0] Frequency Table for BCLK[1:0] ............20 Processor DC Absolute Maximum Ratings ............21 Voltage and Current Specifications..............

  • Page 7: Revision History

    Revision History Revision Description Date -001 • Initial release February 2004 -002 • Added specifications for 3.20 GHz processors with PRB = 1 April 2004 • Added ISGNT/ISLP specifications • Updated thermal diode specifications • Other changes marked with change bars -003 •...
  • Page 8 Error Correcting Code 800 MHz front side bus (FSB) (ECC) • • Binary compatible with applications 144 Streaming SIMD Extensions 2 running on previous members of the Intel (SSE2) instructions microprocessor line • 13 Streaming SIMD Extensions 3 (SSE3) ® •...

  • Page 9: Introduction

    The Pentium 4 processor on 90 nm process, like its predecessor, the Pentium 4 processor in the 478-pin package, is based on the same Intel 32-bit microarchitecture and maintains the tradition of compatibility with IA-32 software.

  • Page 10: Terminology

    Processor Packaging Terminology Commonly used terms are explained here for clarification: ® ® • Intel Pentium 4 processor on 90 nm process — Processor in the FC-mPGA4 package with a 1-MB L2 cache. • Processor — For this document, the term processor is the generic form of the Pentium 4 processor on 90 nm process.

  • Page 11: References

    ® ® Intel Pentium 4 Processor 478-Pin Socket (mPGA478B) Socket http://developer.intel.com/design/ Design Guidelines pentium4/guides/249890.htm Intel ® Architecture Software Developer's Manual ® IA-32 Intel Architecture Software Developer’s Manual Volume 1: Basic Architecture ® IA-32 Intel Architecture Software Developer’s Manual, Volume 2A: Instruction Set Reference, A-M http://www.intel.com/design/...
  • Page 12 Introduction Datasheet...

  • Page 13: Electrical Specifications

    Electrical Specifications Electrical Specifications Power and Ground Pins For clean on-chip power distribution, the processor has 85 VCC (power) and 179 VSS (ground) pins. All power pins must be connected to V , while all VSS pins must be connected to a system ground plane.The processor VCC pins must be supplied by the voltage determined by the VID (Voltage identification) pins.

  • Page 14: Fsb Clock (Bclk[1:0]) And Processor Clocking

    Electrical Specifications 2.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor core frequency is a multiple of the BCLK[1:0] frequency.

  • Page 15: Voltage Identification Definition

    Electrical Specifications Table 3. Voltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0 VID5 VID4 VID3 VID2 VID1 VID0 0.8375 1.2125 0.8500 1.2250 0.8625 1.2375 0.8750 1.2500 0.8875 1.2625 0.9000 1.2750 0.9125 1.2875 0.9250 1.3000 0.9375 1.3125 0.9500 1.3250 0.9625 1.3375 0.9750 1.3500...

  • Page 16: Phase Lock Loop (Pll) Power And Filter

    Electrical Specifications 2.3.1 Phase Lock Loop (PLL) Power and Filter and V are power sources required by the PLL clock generators on the processor CCIOPLL silicon. Since these PLLs are analog, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency).

  • Page 17: Reserved, Unused, And Testhi Pins

    Electrical Specifications Reserved, Unused, and TESTHI Pins All RESERVED pins must remain unconnected. Connection of these pins to V , or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a pin listing of the processor and the location of all RESERVED pins.

  • Page 18: Fsb Signal Groups

    Electrical Specifications FSB Signal Groups The FSB signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers that use GTLREF as a reference level. In this document, the term "GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, "GTL+ Output"...

  • Page 19: Asynchronous Gtl+ Signals

    Electrical Specifications Table 5. Signal Characteristics Signals with R Signals with No R A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[1:0], A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, COMP[1:0], FERR#/PBE#, IERR#, IGNNE#, INIT#, BNR#, BOOTSELECT , BPRI#, D[63:0]#, DBI[3:0]#, LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#, SKTOCC#, SLP#, SMI#, STPCLK#, TDO, DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#, TESTHI[12:0], THERMDA, THERMDC,...

  • Page 20: Fsb Frequency Select Signals (Bsel[1:0])

    Electrical Specifications FSB Frequency Select Signals (BSEL[1:0]) The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 7 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer.

  • Page 21: Absolute Maximum And Minimum Ratings

    Electrical Specifications Absolute Maximum and Minimum Ratings Table 8 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the...

  • Page 22: Voltage And Current Specifications

    Electrical Specifications Table 9. Voltage and Current Specifications Symbol Parameter Unit Notes VID range 1.250 1.400 Loadline A processors Table 10 3,4,5 3.20E GHz (PRB = 1) VID – I (max) * 1.45 mΩ Figure 2 3.40E GHz (PRB = 1) Loadline B processors 2.80A/E GHz (PRB = 0) Table 11...

  • Page 23: Vcc Static And Transient Tolerance For Loadline A

    Electrical Specifications 10. These parameters are based on design characterization and are not tested. Table 10. V Static and Transient Tolerance for Loadline A 1,2,3 Voltage Deviation from VID Setting (V) Icc (A) Maximum Voltage Typical Voltage Minimum Voltage 0.000 -0.019 -0.038 -0.007...

  • Page 24: Vcc Static And Transient Tolerance For Loadline A

    Electrical Specifications Figure 2. V Static and Transient Tolerance for Loadline A Icc [A] VID - 0.000 Maximum VID - 0.038 VID - 0.076 VID - 0.114 Typical VID - 0.152 Minimum VID - 0.190 VID - 0.228 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.11.
  • Page 25 Electrical Specifications Table 11. V Static and Transient Tolerance for Loadline B 1,2,3 Voltage Deviation from VID Setting (V) Icc (A) Maximum Voltage Typical Voltage Minimum Voltage 0.000 -0.025 -0.050 -0.007 -0.033 -0.059 -0.015 -0.041 -0.068 -0.022 -0.049 -0.077 -0.029 -0.058 -0.086 -0.036...

  • Page 26: Vcc Static And Transient Tolerance For Loadline B

    Electrical Specifications Figure 3. V Static and Transient Tolerance for Loadline B Icc [A] VID - 0.000 VID - 0.025 Maximum VID - 0.050 VID - 0.075 VID - 0.100 VID - 0.125 Typical VID - 0.150 Minimum VID - 0.175 VID - 0.200 NOTES: 1.

  • Page 27: Gtl+ Signal Group Dc Specifications

    Electrical Specifications Table 12. GTL+ Signal Group DC Specifications Symbol Parameter Unit Notes 2, 3 Input Low Voltage GTLREF – (0.10 * V 3, 4 Input High Voltage GTLREF + (0.10 * V Output High Voltage 0.90*V Output Low Current /[(0.50*R )+(R Input Leakage Current...

  • Page 28: Pwrgood And Tap Signal Group Dc Specifications

    Electrical Specifications Table 14. PWRGOOD and TAP Signal Group DC Specifications 1, 2 Symbol Parameter Unit Notes Input Hysteresis Input low to high threshold 0.5 * (V 0.5 * (V HYS_MIN HYS_MAX voltage Input high to low threshold 0.5 * (V –...

  • Page 29: Vcc

    Electrical Specifications Table 17. BSEL [1:0] and VID[5:0] DC Specifications Symbol Parameter Unit Notes Ω (BSEL) Buffer On Resistance Ω (VID) Buffer On Resistance Max Pin Current Output Leakage Current µA Voltage Tolerance 3.3 + 5% NOTES: Unless otherwise noted, all specifications in this table apply to all processor frequencies. These parameters are not tested and are based on design simulations.

  • Page 30: Die Voltage Validation

    Electrical Specifications Figure 4. V Overshoot Example Waveform Example Overshoot Waveform VID + 0.050 Time : Overshoot time above VID : Overshoot above VID NOTES: 1. V is measured overshoot voltage. 2. T is measured time duration above VID. 2.11.1 Die Voltage Validation Overshoot events from application testing on real processors must meet the specifications in Table 19...

  • Page 31: Package Mechanical Specifications

    Package Mechanical Specifications Package Mechanical Specifications Package Mechanical Specifications The Pentium 4 processor on 90 nm process is in a Flip-Chip Pin Grid Array (FC-mPGA4) package that interfaces with the motherboard via a mPGA478B socket. The package consists of a processor core mounted on a substrate pin-carrier.

  • Page 32: Package Mechanical Drawing

    Package Mechanical Specifications 3.1.1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 6 Figure 7. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: • Package reference with tolerances (total height, length, width, etc.) •...

  • Page 33: Processor Package Drawing (Sheet 1 Of 2)

    Package Mechanical Specifications Figure 6. Processor Package Drawing (Sheet 1 of 2) Datasheet...

  • Page 34: Processor Package Drawing (Sheet 2 Of 2)

    Package Mechanical Specifications Figure 7. Processor Package Drawing (Sheet 2 of 2) Datasheet...

  • Page 35: Processor Component Keep-Out Zones

    Package Mechanical Specifications 3.1.2 Processor Component Keep-out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keep- out zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate.

  • Page 36: Package Insertion Specifications

    This diagram is intended to aid in the identification of the processor. Figure 8. Processor Top-Side Markings Copyright Info Brand INTEL Product Code PENTIUM® 4 SSPEC/Country of Assy X.XXGHZ / 1M / 800...

  • Page 37: Processor Pinout Coordinates

    Package Mechanical Specifications 3.1.9 Processor Pinout Coordinates Figure 9 shows the top view of the processor pin coordinates. The coordinates are referred to throughout the document to identify processor pins. Figure 9. Processor Pinout Coordinates (Top View) Clocks Async/TAP VCC/VSS 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2...
  • Page 38 Package Mechanical Specifications Datasheet...

  • Page 39: Pin List And Signal Description

    Pin List and Signal Description Pin List and Signal Description This chapter provides the processor pinout and signal description. Processor Pin Assignments The pinout footprint is shown in Figure 10 Figure 11. These figures represent the pinout arranged by pin number. Table 23 provides the pinout arranged alphabetically by signal name and Table 24...

  • Page 40: Pinout Diagram (Top View-Left Side)

    Pin List and Signal Description Figure 10. Pinout Diagram (Top View—Left Side) SKTOCC# Reserved Reserved BCLK1 BCLK0 OPTIMIZED/ DBR# VCCA Reserved COMPAT# ITP_CLK1 TESTHI12 TESTHI0 VSSA VCCIOPLL ITP_CLK0 TESTHI4 TESTHI5 TESTHI2 TESTHI3 SLP# RESET# TESTHI7 GOOD D61# D63# D62# GTLREF TESTHI6 D56# D59#...

  • Page 41: Pinout Diagram (Top View-Right Side)

    Pin List and Signal Description Figure 11. Pinout Diagram (Top View—Right Side) VCCVID VCCVIDLB VID0 VID1 VID2 VID3 VID4 BOOT BSEL0 BSEL1 VID5 VIDPWRGD SELECT BPM0# BPM2# IERR# AP0# BPM1# BPM5# RSP# A35# GTLREF BPM4# BINIT# TESTHI1 BPM3# STPCLK# TESTHI10 A34# INIT# TESTHI9...

  • Page 42: Alphabetical Pin Assignment

    Pin List and Signal Description Table 23. Alphabetical Pin Assignment Table 23. Alphabetical Pin Assignment Signal Buffer Signal Buffer Pin Name Pin # Direction Pin Name Pin # Direction Type Type Source Synch Input/Output BINIT# Common Clock Input/Output Source Synch Input/Output BNR# Common Clock...
  • Page 43 Pin List and Signal Description Table 23. Alphabetical Pin Assignment Table 23. Alphabetical Pin Assignment Signal Buffer Signal Buffer Pin Name Pin # Direction Pin Name Pin # Direction Type Type D26# Source Synch Input/Output DBI3# Source Synch Input/Output D27# Source Synch Input/Output DBR#...
  • Page 44 Pin List and Signal Description Table 23. Alphabetical Pin Assignment Table 23. Alphabetical Pin Assignment Signal Buffer Signal Buffer Pin Name Pin # Direction Pin Name Pin # Direction Type Type RESERVED Power/Other RESERVED Power/Other RESERVED AE21 AA10 Power/Other RESERVED AF24 AA12 Power/Other...
  • Page 45 Pin List and Signal Description Table 23. Alphabetical Pin Assignment Table 23. Alphabetical Pin Assignment Signal Buffer Signal Buffer Pin Name Pin # Direction Pin Name Pin # Direction Type Type Power/Other VCC_SENSE Power/Other Output AF21 Power/Other VCCVID Power/Other Input Power/Other VCCVIDLB Power/Other...
  • Page 46 Pin List and Signal Description Table 23. Alphabetical Pin Assignment Table 23. Alphabetical Pin Assignment Signal Buffer Signal Buffer Pin Name Pin # Direction Pin Name Pin # Direction Type Type Power/Other Power/Other AC11 Power/Other Power/Other AC13 Power/Other Power/Other AC15 Power/Other Power/Other AC17...
  • Page 47 Pin List and Signal Description Table 23. Alphabetical Pin Assignment Table 23. Alphabetical Pin Assignment Signal Buffer Signal Buffer Pin Name Pin # Direction Pin Name Pin # Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...

  • Page 48: Numerical Pin Assignment

    Pin List and Signal Description Table 24. Numerical Pin Assignment Table 24. Numerical Pin Assignment Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type THERMTRIP# Asynch GTL+ Output Power/Other Power/Other Power/Other VSS_SENSE Power/Other Output Power/Other VCC_SENSE...
  • Page 49 Pin List and Signal Description Table 24. Numerical Pin Assignment Table 24. Numerical Pin Assignment Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type Power/Other DSTBN0# Source Synch Input/Output Power/Other Power/Other Power/Other D17# Source Synch Input/Output Power/Other...
  • Page 50 Pin List and Signal Description Table 24. Numerical Pin Assignment Table 24. Numerical Pin Assignment Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type DBI1# Source Synch Input/Output Power/Other D25# Source Synch Input/Output ADSTB0# Source Synch Input/Output...
  • Page 51 Pin List and Signal Description Table 24. Numerical Pin Assignment Table 24. Numerical Pin Assignment Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type DSTBP#2 Source Synch Input/Output A27# Source Synch Input/Output D41# Source Synch Input/Output A32#...
  • Page 52 Pin List and Signal Description Table 24. Numerical Pin Assignment Table 24. Numerical Pin Assignment Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type Power/Other AB22 TESTHI7 Power/Other Input Power/Other AB23 PWRGOOD Power/Other Input Power/Other AB24...
  • Page 53 Pin List and Signal Description Table 24. Numerical Pin Assignment Table 24. Numerical Pin Assignment Signal Buffer Signal Buffer Pin # Pin Name Direction Pin # Pin Name Direction Type Type AD11 Power/Other AE19 Power/Other AD12 Power/Other AE20 Power/Other AD13 Power/Other AE21 RESERVED...

  • Page 54: Alphabetical Signals Reference

    Pin List and Signal Description Alphabetical Signals Reference Table 25. Signal Description (Page 1 of 8) Name Type Description A[35:3]# (Address) define a 2 -byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction.
  • Page 55 BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. ® Refer to the Intel 865G/865GV/865PE/865P Chipset Platform Design Guide for more detailed information. These signals do not have on-die termination. Refer to Section 2.4, and the...
  • Page 56 Pin List and Signal Description Table 25. Signal Description (Page 3 of 8) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents.
  • Page 57 FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting.
  • Page 58 This signal should be left as a no connect on the baseboard to indicate that the OPTIMIZED/ ® ® Input baseboard supports the Intel Pentium 4 processor on 90 nm process. This COMPAT# input has a weak internal pull-up. Datasheet...
  • Page 59 Pin List and Signal Description Table 25. Signal Description (Page 6 of 8) Name Type Description As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its Input/ maximum safe operating temperature. This indicates that the processor Thermal PROCHOT# Output Control Circuit (TCC) has been activated, if enabled.
  • Page 60 VCC are the power pins for the processor. The voltage supplied to these pins is Input determined by the VID[5:0] pins. VCCA provides isolated power for the internal processor core PLLs. Refer to the ® VCCA Input Intel 865G/865GV/865PE/865P Chipset Platform Design Guide for complete implementation details. Datasheet...
  • Page 61 VCCIOPLL provides isolated power for internal processor FSB PLLs. Follow the ® VCCIOPLL Input guidelines for VCCA, and refer to the Intel 865G/865GV/865PE/865P Chipset Platform Design Guide for complete implementation details. VCC_SENSE is an isolated low impedance connection to processor core power...
  • Page 62 Pin List and Signal Description Datasheet...

  • Page 63: Thermal Specifications And Design Considerations

    Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. ® For more information on designing a component level thermal solution, refer to the Intel ® Pentium 4 Processor on 90 nm Process Thermal Design Guidelines.

  • Page 64: Processor Thermal Specifications

    To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. ®...

  • Page 65: Thermal Profile

    Thermal Specifications and Design Considerations Table 27. Thermal Profile Power (W) Maximum Tc (°C) Power Maximum Tc (°C) 43.3 59.0 43.9 59.5 44.5 60.1 45.0 60.7 45.6 61.3 46.2 61.9 46.8 62.4 47.4 63.0 47.9 63.6 48.5 64.2 49.1 64.8 49.7 65.3 50.3...

  • Page 66: Thermal Metrology

    Intel recommends T thermal measurements should be made. For detailed guidelines on ® ® temperature measurement methodology, refer to the Intel Pentium 4 Processor on 90 nm Process Thermal Design Guidelines. Figure 13. Case Temperature (T ) Measurement Location Measure from edge of processor IHS 15.5 mm...

  • Page 67: Processor Thermal Features

    ® ® processor, even when the TCC is active continuously. Refer to the Intel Pentium 4 Processor on 90 nm Process Thermal Design Guidelines for information on designing a thermal solution.

  • Page 68: On-Demand Mode

    Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#. Refer to the Intel Architecture Software Developer's Manuals for specific register and programming details.

  • Page 69: Thermtrip# Signal Pin

    Thermal Specifications and Design Considerations 5.2.4 THERMTRIP# Signal Pin Regardless of whether or not the Thermal Monitor feature is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 25).

  • Page 70: Thermal Diode Parameters

    3.33 3.594 NOTES: Intel does not support or recommend operation of the thermal diode under reverse bias. Characterized at 75 °C. Not 100% tested. Specified by design characterization. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equa-...

  • Page 71: Features

    Features Features This chapter contains power-on configuration options and clock control/low power state descriptions. Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table The sampled information configures the processor for subsequent operation.

  • Page 72: Clock Control And Low Power States

    LINT[1:0] (NMI, INTR). RESET# causes the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT powerdown state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information.

  • Page 73: Stop-Grant State-State 3

    Features 6.2.3 Stop-Grant State—State 3 When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to V ) for minimum power drawn by the termination resistors in this state.

  • Page 74: Sleep State-State 5

    Features 6.2.5 Sleep State—State 5 The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal.

  • Page 75: Boxed Processor Specifications

    Boxed Processor Specifications Boxed Processor Specifications The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.

  • Page 76: Mechanical Specifications

    Boxed Processor Specifications Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 15 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.

  • Page 77: Boxed Processor Fan Heatsink Weight

    The target load applied by the clips to the processor heat spreader for Intel's reference design is 75 ±15 lbf (maximum load is constrained by the package load capability). It is normal to observe a bow or bend in the board due to this compressive load on the processor package and the socket.

  • Page 78: Boxed Processor Retention Mechanism And Heatsink Attach Clip Assembly

    Boxed Processor Specifications 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a processor retention mechanism and a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket. The boxed processor will not ship with retention mechanisms but will ship with the heatsink attach clip assembly.

  • Page 79: Thermal Specifications

    Boxed Processor Specifications Table 31. Fan Heatsink Power and Signal Specifications Description Unit Notes +12 V: 12 volt fan power supply 10.2 13.8 IC: Fan current draw pulses per fan SENSE: SENSE frequency revolution NOTES: Baseboard should pull this pin up to 5 V with a resistor. Figure 19.

  • Page 80: Boxed Processor Fan Heatsink Airspace Keep-Out Requirements (Side 1 View)

    Boxed Processor Specifications boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

  • Page 81: Variable Speed Fan

    Boxed Processor Specifications 7.3.2 Variable Speed Fan The boxed processor fan operates at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If the internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached.

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