Intel 460GX Software Developer’s Manual page 145

All regions, including the two described above, must be checked after GART translation. The GXB
must only allow accesses that are directed to physical memory to reach the SAC. Therefore, the
GXB must force a BINIT#, by asserting its "XBINIT#" output, when it detects an access falling in
any of the following regions:
•
Above the TOM register value (firmware sets TOM to top of physical system memory - this
may be anywhere in memory, as low as 64 MB or as high as 64 GB)
•
Between GAPBASE and GAPTOP registers and not in the SAPIC interrupt delivery region -
firmware must set these two registers to cover the following ranges:
— In High System firmware (fixed range from 4G to 4G-16M).
— In first megabyte of Itanium processor specific (fixed range from 4G-16M to 4G-17M).
— In Itanium processor specific below the Interrupt region (fixed range from 4G-18M to
4G-20M).
— In chipset specific (fixed range from 4G-20M to 4G-32M).
— In any of the nx32M PCI spaces.
Therefore GAPTOP=4G and GAPBASE is the lowest PXB's/GXB's MMBASE in the system.
Note, the SAPIC interrupt delivery area from 4G-17M to 4G-18M must be allowed and specifically
decoded so it will *not* cause a fault.
•
In a MARG with DRAM accesses disabled (the MARGs cover the C, D, E, and F segments).
•
In the VGA region (A_0000-BFFFF) with VGAGE enabled so that this region is directed to
PCI, a PCI access in this range would not have gotten DEVSEL#.
Intel® 460GX Chipset Software Developer's Manual
AGP Subsystem
7-15