Intel 460GX Software Developer’s Manual page 48

Register Descriptions
2.4.6.2 ERRCMD: Error Command Register
Address Offset:
Default Value:
This register provides extended control over the signalling of errors through SERR_OUT#,
XBINIT#, and INTRQ#. These controls are in addition to the defined controls specified in the PCI-
standard PCICMD register for SERR# assertion.
Bits
15
Note: Software should verify that there are no errors pending (by evaluating the ERRSTS register) before
clearing this bit.
Note: This bit is Reserved on side-b and records a value of one only!
14
Note: This bit is Reserved on side-b and records a value of zero only!
13
12
11
10
9:7
6
5:0
2.4.6.3 FEPCI: PCI Bus First Error Status Register
Address Offset:
Default Value:
This register records and latches the first error observed on the PCI bus. Once an error has been
noted in this register, no further updates are allowed. This register is a write-1-to-clear register,
meaning that software must write a 1 to the specific bit location it wishes cleared. The response to
2-28
45h– 46h
8040h
Description
XBINITO: XBinit Override Enable
This bit should always be initially set to 0 by software. If set to 0, XBINIT# may be
asserted by the WXB. The WXB will automatically set this bit after an XBINIT# is
signaled. Default = 1
reserved(0)
IRQE: INTRQ Enable
Controls the reporting of WXB transmitted data errors. If set, the WXB will assert an
INTRQ interrupt for observed PERR# (including IHPC-driven parity errors) and data
parity errors detected in outbound transactions (e.g. Internal Queue Error detected
during read by PCI interface). Default = 0.
ASAPE: Assert SERR# on Address Parity Error
This bit should always be set to 1. When the WXB detects a PCI Address Parity Error
and both SERRE and PERRE are set, SERR# (and SERR_OUT#) will be signaled.
Default = 0.
ASDPE: Assert SERR# on any Data Parity Error
If set, the WXB will assert SERR# (and SERR_OUT#) whenever a data parity error is
detected in an inbound transaction. The SERRE bit in the PCICMD register must also be
set for SERR# (and SERR_OUT#) to be signaled. Default = 0.
ASDTE: Assert SERR# on Discard Timer Expiration
This bit should always be set to 1. When an inbound read Discard Timer Expiration
occurs and SERRE is set, SERR# (and SERR_OUT#) will be signaled. Default = 0.
reserved(0)
reserved(1)
reserved (0)
83h
00h
Size:
Attribute:
Size:
Attribute:
Intel® 460GX Chipset Software Developer's Manual
16 bits
Read/Write
8 bits
Read/Write Clear,
Sticky