Intel 460GX Software Developer’s Manual page 43

3
2
1
0
2.4.4.2 ERRCMD: Error Command Register
Address Offset:
Default Value:
This register provides extended control over the assertion of SERR# beyond the basic controls
specified in the PCI-standard PCICMD register.
Bits
7
6
5
4
3
2
1
0
Intel® 460GX Chipset Software Developer's Manual
Inbound Delayed Read Time-out Flag
Each inbound read request that is accepted and serviced as a delayed read (i.e. the PXB
retries the request) will initiate a watchdog timer (2
has been returned and the timer expires before the requesting master initiates its repeat
request, this flag will be set. This flag may be configured to assert SERR# or PERR# in
the ERRCMD register. This bit remains set until explicitly cleared by software writing
a 1 to this bit.
reserved(0)
Performance Monitor #1 Event Flag
This flag is set when the Performance Monitor #1 requests that an interrupt request be
asserted. The PME and PMR registers
conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will
be asserted. This bit remains set until explicitly cleared by software writing a 1 to this bit.
Performance Monitor #0 Event Flag
This flag is set when the Performance Monitor #0 requests that an interrupt request be
asserted. The PME and PMR registers
conditions that can cause this to occur. While this bit is set, the INT(A,B)RQ# line will
be asserted. This bit remains set until explicitly cleared by software writing a 1 to this bit.
46h
00h
Description
reserved(0)
Assert SERR# on Observed Parity Error
If set, the PXB asserts SERR# if PERR# is observed asserted, and the PXB was not the
asserting agent.
Assert SERR# on Received Data with Parity Error
If set, the PXB asserts SERR# upon receiving PCI data (i.e. an inbound write or outbound
read) with a parity error. This occurs regardless of whether PXB asserts it's PERR# pin.
Assert SERR# on Address Parity Error
If set, the PXB asserts SERR# on detecting a PCI address parity error.
Assert PERR# on Data Parity Error
If set, and the PERRE bit is set in the PCICMD register, the PXB asserts PERR# upon
receiving PCI data with parity errors.
Assert SERR# on Inbound Delayed Read Time-out
Each inbound read request that is accepted and serviced as a delayed read (i.e. the PXB
retries the request) will initiate a watchdog timer (2
enable is set, the PXB will assert SERR# if the data has been returned and the timer
expires before the requesting master initiates its repeat request. Default=0.
reserved(0)
Return Hard Fail Upon Generating Master Abort
If set, the PXB will return a Hard Fail response through the SAC to the system bus after
generating a master abort time-out for an outbound transaction placed on the PCI bus. If
cleared, the PXB will return a normal response (with data of all 1's for a read). In either
case, an error flag is set in the PCISTS register. Default=0.
Register Descriptions
15
cycles, per the PCI spec). If the data
(Section 2.5.3.3, Section 2.5.3.2) describe the
(Section 2.5.3.3, Section 2.5.3.2) describe the
Size:
Attribute:
15
cycles, per the PCI spec). If this
8 bits
Read/Write
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