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Summary of Contents for Intel UPI- 41A
- Page 1 Microprocessor Peripherals UPI- 41A 41AH 42 42AH User’s Manual October 1993 Order Number 231318-006...
- Page 2 Information in this document is provided in connection with Intel products Intel assumes no liability whatsoev- er including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products...
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Page 3: Table Of Contents
Microprocessor Peripherals UPI-41A 41AH 42 42AH User’s Manual CONTENTS CONTENTS PAGE PAGE Reset CHAPTER 1 INTRODUCTION Data Bus Buffer Interface Registers for Multiprocessor System Interface Configurations Input Output Interface Powerful 8-Bit Processor Ports 1 and 2 Special Instruction Set Features Ports 4 5 6 and 7 Preprogrammed UPI’s Development Support... -
Page 5: Upi-41A 41Ah 42 42Ah User's Manual
Programmable Interval Timer With the introduction of the Universal Peripheral In- 8257 (DMA) Programmable DMA Controller terface (UPI) microcomputer Intel has taken the intel- 8259 Programmable Interrupt ligent peripheral concept a step further by providing an intelligent controller that is fully user programmable It... - Page 6 128 x 8 RAM 128 x 8 RAM 256 x 8 RAM Set Security Feature Signature Row Feature 32 Bytes with 1 Test Code Checksum 2 Intel Signature 3 Security Byte 4 User Signature PROGRAMMING UPI-41A UPI-42 UPI-41AH UPI-42AH 12 5V...
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Page 7: Interface Registers For Multiprocessor
UPI-41A 41AH 42 42AH USER’S MANUAL HMOS processing has been applied to the UPI family isters are the Data Bus Buffer Input (DBBIN) Data to allow for additional performance and memory capa- Bus Buffer Output (DBBOUT) and Status (STATUS) bility while reducing costs The UPI-41A 41AH 42 registers The host processor may read data from 42AH are all pin and software compatible This allows DBBOUT or write commands and data into DBBIN... -
Page 8: Special Instruction Set Features
UPI-41A 41AH 42 42AH USER’S MANUAL 231318– 49 231318–47 231318 –2 231318 – 3 8741A 8741AH 8742AH 8041AH 8042AH D8742 Electrically Electrically Programmed Electrically Programmable Programmed Programmable Light Erasable OTP EPROM Light Erasable EPROM EPROM Figure 1-2 Pin Compatible ROM EPROM Versions For BDC Arithmetic SPECIAL INSTRUCTION SET Decimal Adjust A... -
Page 9: Preprogrammed Upi's
Figure 1-4 8243 I O Expander Interface The 8242AH 8292 and 8294 are 8042AH’s that are programmed by Intel and sold as standard peripherals Intel offers a complete line of factory programmed key- On-Chip Memory board controllers These devices contain firmware de- veloped by Phoenix Technologies Ltd and Award Soft- The UPI’s 64 128 256 bytes data memory include dual... -
Page 10: Development Support
UPP PROM program- Universal PROM Programmer UPP Series mer already mentioned The combination of device fea- Application Engineers tures and Intel development support make the UPI an ideal component for low-speed peripheral control appli- Training Courses cations... -
Page 11: Chapter 2 Functional Description
UPI-41A 41AH 42 42AH USER’S MANUAL CHAPTER 2 FUNCTIONAL DESCRIPTION The UPI microcomputer is an intelligent peripheral ory the 8741A 8742 (with UV erasable program mem- controller designed to operate in iAPX-86 88 MCS-85 ory) and the 8041AH 8042AH These devices are so MCS-80 MCS-51 and MCS-48 systems The UPI’s ar- similar that they can be considered identical under chitecture illustrated in Figure 2-1 is based on a low... - Page 12 UPI-41A 41AH 42 42AH USER’S MANUAL 231318 –7 Figure 2-2 Pin Configuration 231318 – 8 Figure 2-3 Logic Symbol...
- Page 13 UPI-41A 41AH 42 42AH USER’S MANUAL The following section summarizes the functions of each UPI pin NOTE that several pins have two or more functions which are described in separate paragraphs Table 2-1 Pin Description Symbol Pin No Type Name and Function –D 12 –...
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Page 14: Cpu Section
UPI-41A 41AH 42 42AH USER’S MANUAL The following sections provide a detailed functional de- In a typical operation data from the accumulator is scription of the UPI microcomputer Figure 2-4 illus- combined in the ALU with data from some other trates the functional blocks within the UPI device source on the UPI-41A 41AH 42 42AH internal bus (such as a register or an I O port) The result of an... -
Page 15: Program Memory
UPI-41A 41AH 42 42AH USER’S MANUAL PROGRAM MEMORY INTERRUPT VECTORS The UPI-41A 41AH 42 42AH microcomputer has 1) Location 0 1024 2048 8-bit words of resident read-only memory Following a RESET input to the processor the next for program storage Each of these memory locations is instruction is automatically fetched from location 0 directly addressable by a 10-bit program counter De- 2) Location 3... -
Page 16: Program Counter
UPI-41A 41AH 42 42AH USER’S MANUAL accessed intermediate results Other locations in data interrupt processing registers in bank 0 can be accessed memory are addressed indirectly by using R or R indirectly using R and R specify the desired address If register bank 1 is not used registers 24 –... -
Page 17: Program Status Word
UPI-41A 41AH 42 42AH USER’S MANUAL An interrupt or Call to a subroutine causes the contents Carry of the program counter to be stored in one of the 8 Auxiliary Carry register pairs of the program counter stack Flag 0 Register Bank Select DATA STACK... -
Page 18: Oscillator And Timing Circuits
UPI-41A 41AH 42 42AH USER’S MANUAL Table 2-2 lists the internal conditions which are testable which UPI is used Refer to Table 1 1 Pins XTAL 1 and indicates the condition which will cause a jump In and XTAL 2 are input and output (respectively) of a all cases the destination address must be within the high gain amplifier stage A crystal or inductor and page of program memory (256 locations) in which the... - Page 19 UPI-41A 41AH 42 42AH USER’S MANUAL Table 2-3 Instruction Timing Diagram CYCLE 1 CYCLE 2 Instruction Fetch Increment Increment Read Port IN A Pp Instruction Program Counter Timer Fetch Increment Increment Output OUTL Pp A Instruction Program Counter Timer To Port Fetch Increment Increment...
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Page 20: Interval Timer Event Counter
UPI-41A 41AH 42 42AH USER’S MANUAL Cycle Counter INTERVAL TIMER EVENT COUNTER The output of the state counter is divided by 5 in the The UPI-41A 41AH 42 42AH has a resident 8-bit cycle counter to generate a signal which defines a ma- timer counter which has several software selectable chine cycle This signal is call SYNC and is available modes of operation As an interval timer it can gener-... -
Page 21: Test Inputs
UPI-41A 41AH 42 42AH USER’S MANUAL 8-bit event counter The Start Counter (STRT CNT) Timer Mode instruction controls an internal switch which connects TEST 1 through an edge detector to the 8-bit internal The STRT T instruction connects the internal clock to counter Note that this instruction does not inhibit the the counter input and enables the counter The input testing of TEST 1 via conditional Jump instructions... -
Page 22: Interrupts
UPI-41A 41AH 42 42AH USER’S MANUAL The test imputs are TTL compatible An external logic Figure 2-14 illustrates the internal interrupt logic An signal connected to one of the test inputs will be sam- IBF interrupt request is generated whenever WR and pled at the time the appropriate conditional jump in- CS are both low regardless of whether interrupts are struction is executed The path of program execution... -
Page 23: Reset
UPI-41A 41AH 42 42AH USER’S MANUAL Location 3 in program memory should contain an un- sition of the TEST 1 input pin Also if an IBF interrupt conditional jump to the beginning of the IBF interrupt occurs during servicing of the timer counter interrupt service routine elsewhere in program memory At the it will remain pending until the end of the service rou- end of the service routine an RETR (Return and Re-... -
Page 24: Data Bus Buffer
UPI-41A 41AH 42 42AH USER’S MANUAL 231318 –20 Figure 2-15 External Reset Configuration The RESET input performs the following functions trol and is completely asynchronous to the external processor timing This allows the UPI software to han- Disables Interrupts dle peripheral control tasks independent of the main Clears Program Counter to Zero processor while still maintaining a data interface with Clears Stack Pointer... -
Page 25: System Interface
UPI-41A 41AH 42 42AH USER’S MANUAL UPI Bus Contents During Status Read 231318 –21 Figure 2-16 Data Bus Buffer Configuration This is a general purpose flag which can be cleared CHIP SELECT signal used to enable one 8041AH or toggled under UPI software control The flag is out of several connected to a common bus used to transfer UPI status information to the mas- ter processor... -
Page 26: Input Output Interface
UPI-41A 41AH 42 42AH USER’S MANUAL 231318 –22 Figure 2-17 Interface to 8080 System Bus Table 2-4 Data Transfer Controls Command Write CS RD WR A During any write (Table 2-4) the state of the A input is latched into the status register in the F (command Read DBBOUT register data) flag location This additional bit is used to signal... -
Page 27: Ports 4 5 6 And 7
UPI-41A 41AH 42 42AH USER’S MANUAL OUTL Pp A instruction is latched and remains un- An external TTL device connected to the pin has suffi- changed until it is rewritten Input data is sampled at cient current sinking capability to pull-down the pin to the time the IN A Pp instruction is executed There- the low state An IN A Pp instruction will sample the fore input data must be present at the PORT until read... - Page 28 UPI-41A 41AH 42 42AH USER’S MANUAL instructions This feature saves program space and de- Multiple 8243’s can be connected to the PORT 2 inter- sign time and improves the bit handling capability of face In normal operation only one of the 8243’s would the UPI-41A 41AH 42 42AH be active at the time an Input or Output command is executed The upper half of PORT 2 is used to provide...
- Page 29 UPI-41A 41AH 42 42AH USER’S MANUAL 231318 –25 231318 –26 Figure 2-20 8243 Expander Interface 231318 –27 Figure 2-21 Multiple 8243 Expansion...
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Page 30: Chapter 3 Instruction Set
UPI-41A 41AH 42 42AH USER’S MANUAL CHAPTER 3 INSTRUCTION SET The UPI-41A 41AH 42 42AH Instruction Set is op- accumulator and the on-board timer counter the code-compatible with the MCS-48 set except for the Status Register (STS) or the Program Status Word elimination of external program and data memory in- (PSW) Transfers to the STS register alter bits 4 –... - Page 31 UPI-41A 41AH 42 42AH USER’S MANUAL operations Both Carry and Auxiliary Carry are part of in a single instruction which is useful in implementing a the Program Status Word (PSW) and are stored in the loop counter This instruction can designate any of the stack during subroutine calls The F and F flags are...
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Page 32: Instruction Set Description
UPI-41A 41AH 42 42AH USER’S MANUAL external clock applied to the TEST 1 pin The instruc- UPI-41A 41AH 42 42AH peripheral interface via tion executed determines which clock source is used A four PORT 2 lines which form an expander bus The single instruction stops the counter whether it is operat- 8243 ports have their own AND and OR instructions ing with an internal or an external clock source In... - Page 33 UPI-41A 41AH 42 42AH USER’S MANUAL Table 3-2 Instruction Set Summary Mnemonic Description Bytes Cycle Mnemonic Description Bytes Cycle ACCUMULATOR DATA MOVES (Continued) ADD A Rr Add register to A MOVP A Move to A from current ADD A Add data memory to A page ADD A data...
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Page 34: Alphabetic Listing
UPI-41A 41AH 42 42AH USER’S MANUAL ALPHABETIC LISTING ADD A Rr Add Register Contents to Accumulator 0 1 1 0 Opcode The contents of register ‘r’ are added to the accumulator Carry is affected (Rr) 0– 7 Example ADDREG ADD A R6 ADD REG 6 CONTENTS TO ACC ADD A... - Page 35 UPI-41A 41AH 42 42AH USER’S MANUAL ADDC A Rr Add Carry and Data Memory Contents to Accumulator Opcode 0 1 1 1 0 0 0 r The content of the carry bit is added to accumulator location 0 Then the contents of the standard data memory location addressed by register ‘r’...
- Page 36 UPI-41A 41AH 42 42AH USER’S MANUAL ANL A data Logical AND Accumulator With Immediate Mask Opcode 0 1 0 1 0 0 1 1 This is a 2-cycle instruction Data in the accumulator is logically ANDed with an immediate- ly-specified mask (A) AND data Example ANDID ANL A...
- Page 37 UPI-41A 41AH 42 42AH USER’S MANUAL CALL address Subroutine Call Opcode 0 1 0 0 This is a 2-cycle instruction The program counter and PSW bits 4 – 7 are saved in the stack The stack pointer (PSW bits 0 – 2) is updated Program control is then passed to the location specified by ‘address’...
- Page 38 UPI-41A 41AH 42 42AH USER’S MANUAL CLR F0 Clear Flag 0 Opcode 1 0 0 0 0 1 0 1 flag is cleared to zero CPL A Complement Accumulator Opcode 0 0 1 1 0 1 1 1 The contents of the accumulator are complemented This is strictly a one’s complement Each one is changed to zero and vice-versa NOT (A) Example...
- Page 39 UPI-41A 41AH 42 42AH USER’S MANUAL DA A Decimal Adjust Accumulator Opcode 0 1 0 1 0 1 1 1 The 8-bit accumulator value is adjusted to form two 4-bit Binary Coded Decimal (BCD) digits following the binary addition of BCD numbers The carry bit C is affected If the contents of bits 0 –...
- Page 40 UPI-41A 41AH 42 42AH USER’S MANUAL DIS TCNTI Disable Timer Counter Interrupt Opcode 0 0 1 1 0 1 0 1 The timer counter interrupt is disabled Any pending timer interrupt request is cleared The interrupt sequence is not initiated by an overflow but the timer flag is set and time accumula- tion continues DJNZ Rr address Decrement Register and Test Opcode...
- Page 41 UPI-41A 41AH 42 42AH USER’S MANUAL EN I Enable IBF Interrupt Opcode 0 0 0 0 0 1 0 1 The Input Buffer Full interrupt is enabled A low signal on WR and CS initiates the interrupt sequence EN TCNTI Enable Timer Counter Interrupt Opcode 0 0 1 0 0 1 0 1...
- Page 42 UPI-41A 41AH 42 42AH USER’S MANUAL INC Rr Increment Register Opcode 0 0 0 1 The contents of working register ‘r’ are incremented by one (Rr) (Rr) 0– 7 Example INCR0 INC R0 INCREMENT ADDRESS REG 0 Rr Increment Data Memory Location 0 0 0 1 0 0 0 r Opcode...
- Page 43 UPI-41A 41AH 42 42AH USER’S MANUAL JF1 address Jump If C D Flag (F1) Is Set Opcode 0 1 1 1 0 1 1 0 This is a 2-cycle instruction Control passes to the specified address if the C D flag (F ) is set to one addr...
- Page 44 UPI-41A 41AH 42 42AH USER’S MANUAL JNTO address Jump if TEST 0 is Low Opcode 0 0 1 0 0 1 1 0 This is a 2-cycle instruction Control passes to the specified address if the TEST 0 signal is low Pin is sampled during SYNC addr if T...
- Page 45 UPI-41A 41AH 42 42AH USER’S MANUAL JTO address Jump If TEST 0 Is High Opcode 0 0 1 1 0 1 1 0 This is a 2-cycle instruction Control passes to the specified address if the TEST 0 signal is high ( 1) Pin is sampled during SYNC addr...
- Page 46 UPI-41A 41AH 42 42AH USER’S MANUAL MOV A Rr Move Register Contents to Accumulator Opcode 1 1 1 1 Eight bits of data are moved from working register ‘r’ into the accumulator (Rr) 0– 7 Example MAR MOV A R3 MOVE CONTENTS OF REG 3 TO ACC MOV A...
- Page 47 UPI-41A 41AH 42 42AH USER’S MANUAL MOV Rr A Move Accumulator Contents to Register Opcode 1 0 1 0 The contents of the accumulator are moved to register ‘r’ (Rr) 0– 7 Example MRA MOV R0 A MOVE CONTENTS OF ACC TO REG 0 MOV Rr data Move Immediate Data to Register...
- Page 48 UPI-41A 41AH 42 42AH USER’S MANUAL MOV STS A Move Accumulator Contents to STS Register Opcode 1 0 0 1 0 0 0 0 The contents of the accumulator are moved into the status register Only bits 4 – 7 are affected (STS 4–7 4–7...
- Page 49 UPI-41A 41AH 42 42AH USER’S MANUAL MOVP A A Move Current Page Data to Accumulator Opcode 1 0 1 0 0 0 1 1 This is a 2-cycle instruction The contents of the program memory location addressed by the accumulator are moved to the accumulator Only bits 0 – 7 of the program counter are affected limiting the program memory reference to the current page The program counter is restored following this operation ((A))
- Page 50 UPI-41A 41AH 42 42AH USER’S MANUAL ORL A Rr Logical OR Accumulator With Memory Mask Opcode 0 1 0 0 0 0 0 r Data in the accumulator is logically ORed with the mask contained in the data memory location referenced by register ‘r’ bits 0 – 7 (A) OR ((Rr)) 0–...
- Page 51 UPI-41A 41AH 42 42AH USER’S MANUAL OUTL Pp A Output Accumulator Data to Port 1 and 2 Opcode 0 0 1 1 1 0 p This is a 2-cycle instruction Data residing in the accumulator is transferred (written) to port ‘p’...
- Page 52 UPI-41A 41AH 42 42AH USER’S MANUAL RLC A Rotate Left Through Carry Opcode 1 1 1 1 0 1 1 1 The contents of the accumulator are rotated left one bit Bit 7 replaces the carry bit the carry bit is rotated into the bit 0 position 0–...
- Page 53 UPI-41A 41AH 42 42AH USER’S MANUAL SEL RB0 Select Register Bank 0 Opcode 1 1 0 0 0 1 0 1 PSW BIT 4 is set to zero References to working registers 0 – 7 address data memory locations 0 – 7 This is the recommended setting for normal program execution (BS) SEL RB1 Select Register Bank 1 Opcode...
- Page 54 UPI-41A 41AH 42 42AH USER’S MANUAL STOP TCNT Stop Timer Event Counter Opcode 0 1 1 0 0 1 0 1 This instruction is used to stop both time accumulation and event counting Example Disable interrupt but jump to interrupt routine after eight overflows and stop timer Count overflows in register 7 START DIS TCNTI DISABLE TIMER INTERRUPT...
- Page 55 UPI-41A 41AH 42 42AH USER’S MANUAL SWAP A Swap Nibbles Within Accumulator Opcode 0 1 0 0 0 1 1 1 Bits 0 – 3 of the accumulator are swapped with bits 4-7 of the accumulator 4–7 0–3 Example Pack bits 0 – 3 of locations 50-51 into location 50 PCKDIG MOV R0 MOVE ‘50’...
- Page 56 UPI-41A 41AH 42 42AH USER’S MANUAL XCHD A Rr Exchange Accumulator and Data Memory 4-bit Data Opcode 0 0 1 1 0 0 0 r This instruction exchanges bits 0 – 3 of the accumulator with bits 0 – 3 of the data memory location addressed by bits 0 –...
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Page 57: Chapter 4 Single-Step And Programming Power-Down Modes
UPI-41A 41AH 42 42AH USER’S MANUAL CHAPTER 4 SINGLE-STEP AND PROGRAMMING POWER-DOWN MODES Figure 4-1 illustrates a recommended circuit for single- SINGLE-STEP step operation while Figure 4-2 shows the timing rela- tionship between the SYNC output and the SS input The UPI family has a single-step mode which allows During single-step operation PORT 1 and part of the user to manually step through his program one in-... - Page 58 UPI-41A 41AH 42 42AH USER’S MANUAL 231318 –30 Figure 4-3 Latching Port Data 5) To stop the processor at the next instruction SS must Timing be brought low again before the next SYNC pulse the circuit in Figure 4-1 uses the trailing edge of the The sequence of single-step operation is as follows previous pulse If SS is left high the processor re- 1) The processor is requested to stop by applying a low...
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Page 59: External Access
UPI-41A 41AH 42 42AH USER’S MANUAL nal data RAM in the low-power mode Thus the con- EXTERNAL ACCESS tents of RAM can be maintained and the device draws The UPI family has an External Access mode (EA) only 10 to 15% of its normal power which puts the processor into a test mode This mode The V pin serves as the 5V power supply pin for all... -
Page 60: Chapter 5 System Operation
UPI-41A 41AH 42 42AH USER’S MANUAL CHAPTER 5 SYSTEM OPERATION BUS INTERFACE Reading the DBBOUT Register The sequence for reading the DBBOUT register is The UPI-41A 41AH 42 42AH Microcomputer func- shown in Figure 5-2 This operation causes the 8-bit tions as a peripheral to a master processor by using the contents of the DBBOUT register to be placed on the data bus buffer registers to handle data transfers The... -
Page 61: Design Examples
UPI-41A 41AH 42 42AH USER’S MANUAL 231318– 35 231318 –36 Figure 5-4 Writing Data to DBBIN Figure 5-5 Writing Commands to DBBIN Write Data to DBBIN DESIGN EXAMPLES The sequence for writing data to the DBBIN register is 8085AH Interface shown in Figure 5-4 This operation causes the system Data Bus contents to be transferred to the DBBIN reg- Figure 5-6 illustrates an 8085AH system using a UPI-... - Page 62 UPI-41A 41AH 42 42AH USER’S MANUAL 231318 –37 Figure 5-6 8085AH-UPI System 231318 –38 Figure 5-7 8088-UPI Minimum Mode System...
- Page 63 UPI-41A 41AH 42 42AH USER’S MANUAL 231318 –39 Figure 5-8 8086-UPI Maximum Mode Systems 8282 latches providing separate address and data buses The A and CS inputs are direct connections to the The address bus is 20-lines wide and the data bus is 16- 8080 address bus In larger systems however either of lines wide Multiplexed control lines are decoded by the these inputs may be decoded from the 16 address lines...
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Page 64: General Handshaking Protocol
UPI-41A 41AH 42 42AH USER’S MANUAL 231318 –40 Figure 5-9 8080A-UPI Interface 231318 –41 Figure 5-10 8048-UPI Interface UPI’s when data transfer occurs The UPI’s are pro- CS A (0 0 1) or (0 0 0)) If A 1 write grammed to handle isolated tasks and since they oper- command word set F If A... - Page 65 UPI-41A 41AH 42 42AH USER’S MANUAL 231318 –42 Figure 5-11 Distributed Processor System...
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Page 66: Chapter 6 Applications
UPI-41A 41AH 42 42AH USER’S MANUAL CHAPTER 6 APPLICATIONS cient because the UPI instruction set includes individu- ABSTRACTS al bit set clear operations and expander PORTs 4 – 7 can be directly addressed with single 2-byte instruc- The UPI-41A 41AH 42 42AH is designed to fill a tions Also accumulator bits can be tested in a single wide variety of low to medium speed peripheral inter- operation Scan time for 128 keys is about 10 ms Each... - Page 67 UPI-41A 41AH 42 42AH USER’S MANUAL available to control a 16-digit 7-segment display The face port and asynchronous data buffer registers allow UPI can also be programmed to recognize special com- it to connect directly to this type of system for efficient binations of characters such as commands then two-way data transfer...
- Page 68 UPI-41A 41AH 42 42AH USER’S MANUAL The 8295 Printer Controller is an example of an UPI Universal I O Interface preprogrammed as a dot matrix printer interface Figure 6-4 shows an I O interface design based on the UPI This configuration includes 12 parallel I O lines Tape Cassette Controller and a serial (RS232C) interface for full duplex data transfer up to 1200 baud This type of design can be...
- Page 69 Microcontroller Handbook are avail- interrupt at the proper time for sampling the serial bit able through the Intel Literature Department stream This eliminates the need for software timing 231318 –46...