End Of Interrupt Operation - Intel 460GX Software Developer’s Manual

For CNTRL-2, ICW3 is the slave identification code used during an interrupt acknowledge cycle.
CNTRL-1 broadcasts a code to CNTRL-2 over three internal cascade lines if an IRQ[x] line from
CNTRL-2 won the priority arbitration on the master controller and was granted an interrupt
acknowledge by the CPU. CNTRL-2 compares this identification code to the value stored in
ICW3, and if the code is equal to bits [2:0] of ICW3, CNTRL-2 assumes responsibility for
broadcasting the interrupt vector during the second interrupt acknowledge cycle pulse.
ICW4 must be programmed on both controllers. At the very least, bit 0 must be set to a 1 to
indicate that the controllers are operating in an Intel Architecture-based system.
15.2.1.2 Operation Command Words (OCWs)
These are the command words which dynamically reprogram the Interrupt Controller to operate in
various interrupt modes. Any interrupt lines can be masked by writing an OCW1. A 1 written in
any bit of this command word will mask incoming interrupt requests on the corresponding IRQx
line.
OCW2 is used to control the rotation of interrupt priorities when operating in the rotating priority
mode and to control the End of Interrupt (EOI) Function of the controller.
OCW3 is used to set up reads of the ISR and IRR, to enable or disable the Special Mask Mode
(SMM), and to set up the interrupt controller in polled interrupt mode. The OCWs can be written
into the Interrupt Controller any time after initialization.
15.2.2

End of Interrupt Operation

15.2.2.1 End of Interrupt (EOI)
The In Service (IS) bit can be set to 0 automatically following the trailing edge of the second
INTA# pulse (when AEOI bit in ICW1 is set to 1) or by a command word that must be issued to the
Interrupt Controller before returning from a service routine (EOI command). An EOI command
must be issued twice with this cascaded interrupt controller configuration, once for the master and
once for the slave.
There are two forms of EOI commands: Specific and Non-specific. When the Interrupt Controller
is operated in modes which preserve the fully nested structure, it can determine which IS bit to set
to 0 on EOI. When a non-Specific EOI command is issued, the Interrupt Controller will
automatically set to 0 the highest IS bit of those that are set to 1, since in the fully nested mode the
highest IS level was necessarily the last level acknowledged and serviced. A non-specific EOI can
be issued with OCW2 (EOI=1, SL=0, R=0).
When a mode is used which may disturb the fully nested structure, the Interrupt Controller may no
longer be able to determine the last level acknowledged. In this case a Specific End of Interrupt
must be issued which includes as part of the command the IS level to be reset. A specific EOI can
be issued with OCW2 (EOI=1, SL=1, R=0, and LO-L2 is the binary level of the IS bit to be set to
0).
It should be noted that an IS bit that is masked by an IMR bit will not be cleared by a non-specific
EOI if the Interrupt Controller is in the Special Mask Mode.
15.2.2.2 Automatic End of Interrupt (AEOI) Mode
If AEOI=1 in ICW4, then the Interrupt Controller will operate in AEOI mode continuously until
reprogrammed by ICW4. Note that reprogramming ICW4 implies that ICW1, ICW2, and ICW3
must be reprogrammed first, in sequence. In this mode, the Interrupt Controller will automatically
Intel® 460GX Chipset Software Developer's Manual
PCI/LPC Bridge Description
15-3