Ide Configuration; Pci Configuration Registers (Function 1); Pci Configuration Registers-Function 1 (Ide Interface) - Intel 460GX Software Developer’s Manual

9.2

IDE Configuration

The IFB PCI function 1 contains an IDE Controller capable of standard Programmed I/O (PIO)
transfers as well as Bus Master transfer capability. It also supports the "Ultra DMA/33"
synchronous DMA mode of data transfer.
9.2.1

PCI Configuration Registers (Function 1)

Table 9-2. PCI Configuration Registers–Function 1 (IDE Interface)
Configuration Offset
00–01h
02–03h
04–05h
06–07h
08h
09-0Bh
0Ch
0Dh
0Eh
0F–1Fh
20–23h
24–3Fh
40–43h
44h
45–47h
48h
49h
4A–4Bh
4C–F7h
F8-FBh
FC-FFh
Intel® 460GX Chipset Software Developer's Manual
Mnemonic
VID Vendor Identification
DID Device Identification
PCICMD PCI Command
PCISTS PCI Device Status
RID Revision Identification
CLASSC Class Code
– Reserved
MLT Master Latency Timer
HEDT Header Type
– Reserved
BMIBA Bus Master Interface Base Address
– Reserved
IDETIM IDE Timing
SIDETIM Slave IDE Timing
– Reserved
SDMACTL Synchronous DMA Control
– Reserved
SDMATIM Synchronous DMA Timing
– Reserved
--- Manufacturer's ID
--- Reserved
IFB Register Mapping
Register Register Access
RO
RO
R/W
R/W
RO
RO
–
R/W
RO
–
R/W
–
R/W
R/W
–
R/W
–
R/W
–
---
---
9-3