Intel 460GX Software Developer’s Manual page 121

6.11.4.1 GXB Error Signals
The GXB has 2 error signals: XBINIT# and XINTR#.
6.11.4.1.1 GXB_XBINIT#
XBINIT# is used to signal a fatal error. All header errors are fatal, since the GXB and SAC are out
of sync with each other at that point. Data parity errors may be considered fatal in some systems.
For graphics, the error may be in a texture or some field that is a transient screen blip. The OEM
may configure the system to BINIT# on data parity errors or not.
XBINIT# is held active until XRST# is asserted. On XRST#, GXBCTL[7] (XBINIT# enable) is
reset and thus XBINIT# is deasserted. After reset, firmware will log and clear any pending error
registers. It will then enable GXBCTL[7] so that future errors will be reported. Pending bits in the
FERR or NERR registers that were not cleared by firmware will not cause a new BINIT# when
GXBCTL[7] is enabled. Only errors that occur after GXBCTL[7] is enabled will cause the
XBINIT# pin to be asserted.
6.11.4.1.2 XINTR#
XINTR# is used to signal non-fatal errors on the bus. The SERR# signal on the AGP bus will be
OR'ed with internal GXB signals to create XINTR#. The system designer may take this signal and
use it to force an interrupt, handle it like an NMI or SERR#, or even choose to ignore it.
XINTR# is held asserted until all internal conditions which cause INT# are cleared. So software
must handle all errors and then do an EOI to the interrupt controller.
6.11.4.2 GXB Errors
The GXB will flag the following errors. See
6.11.4.2.1 PCI Interface Errors
•
SERR# Observed - Set when the GXB sees SERR# that was asserted by the graphics card.
This is not set if the GXB drove SERR#.
•
PERR# Observed - Set when the GXB sees PERR# that was asserted by the graphics card.
This is not set if the GXB drove PERR#.
•
Discard Timer Expiration - Set when the 2
delayed read is returned to the GXB. If the card doesn't re-access the data in 2
an error is flagged.
•
Non-Configuration Master Abort - Sets bits in both PCISTS and in FERR_PCI. This error
occurs when the GXB is the master for a PCI transaction and there is a master abort (the card
doesn't assert DEVSEL#). This only occurs on non-configuration cycles, since a master abort
is not considered an error on configuration cycles. This error will not cause an interrupt or
BINIT#. Reads will return 1's for DW accesses, or a Hard Fail (HF) for reads that are greater
than a DW. Writes of 1 DW will return a normal write-complete. Writes of more than 1 DW
will return a HF on the write-complete. If there is a master abort on the write then the rest of
the data for that transaction is dropped. Writes using the Fast-write protocol may generate a
master abort.
•
PCISTS Error Logged - Set when any error bit, except RMA (bit 13), in PCISTS is set. This
includes bits 15, 12 or 8. Setting this bit in FERR_PCI does not cause an interrupt or BINIT#.
Intel® 460GX Chipset Software Developer's Manual
Data Integrity and Error Handling
Table 6-1 for the behavior of each error.
15
timer expires. The timer starts when the data for a
15
clocks, then
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