Intel 460GX Software Developer’s Manual page 39

5
4
3:0
2.4.2.23 PVD_D_FERR: Data on First PVD Parity Error
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the data associated with the first parity error detected on the PVD
bus.
Bits
63:0
2.4.2.24 PVD_PAR_FERR: Parity on First PVD Parity Error
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the data associated with the first parity error detected on the PVD
bus.
Bits
7:4
3:0
2.4.2.25 PVD_TXINFO_FERR: TXINFO on First PVD Parity Error
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records the ITID and failing chunk corresponding to the first double-byte parity
detected by private bus interface in the SDC.
Bits
15:9
8:6
5:0
Intel® 460GX Chipset Software Developer's Manual
Memory Bus A ECC correction/detection enable.
Memory Bus B ECC correction/detection enable.
Double byte parity mask for 128 bits of data.
04h
D0-D7h
0
Description
PVD - Private Data Bus data.
04h
D8h
0
Description
reserved(0)
Double–byte parity of error
04h
D9-DAh
00h
Description
reserved(0)
DC - Data Chunk of ITID.
ITID - ITID of error.
Size: 64 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 8 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 16 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Register Descriptions
2-19