Intel 460GX Software Developer’s Manual page 33

This register records and latches the data corresponding to the first SEC detected by memory
interface 1 in the SDC.
Bits
63:0
2.4.2.8 SEC1_ECC_FERR: ECC on First Memory Card A SEC
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the ECC checkbits corresponding to the first SEC detected by
memory interface 1 in the SDC.
Bits
7:0
2.4.2.9 SEC1_TXINFO_FERR: TXINFO on First Memory Card A SEC
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records the ITID and failing chunk corresponding to the first SEC detected by
memory interface 1 in the SDC.
Bits
15:9
8:6
5:0
2.4.2.10 DED1_D_FERR: Data on First Memory Card A DED
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the data corresponding to the first DED detected by memory
interface 1 in the SDC.
Bits
63:0
Intel® 460GX Chipset Software Developer's Manual
Description
DE - System Data of Error.
04h
68h
00h
Description
ECC - ECC of Error.
04h
69-6Ah
00h
Description
reserved(0)
DC - Data Chunk of error.
ITID - ITID of error.
04h
70-77h
0
Description
DE - System Data of Error.
Size: 8 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 16 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 64 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Register Descriptions
2-13