Page 1 ® ® Intel Pentium 4 Processor in the 478-pin Package / ® Intel 850 Chipset Family Platform Design Guide January 2003 Document Number: 249888-008...
Page 2 C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel, Intel logo, Pentium, and Intel Netburst are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
Page 3: Table Of Contents
Platform Clock Routing Guidelines ................... 39 Routing Guidelines for System Bus Clocks ............41 BCLK[1:0] Frequency Select ................46 ® 4.2.1 100 MHz Operation – Intel 82850 Chipset .......... 46 ® 4.2.2 133 MHz Operation – Intel 82850E Chipset........47 Routing Guidelines for Rambus RDRAM* Device Clocks ........
Page 4 Topologies..................... 72 5.4.1.1 Topology 1: Asynchronous GTL+ Signals Driven by the Processor ................72 ® 5.4.1.2 Topology 2: Asynchronous GTL+ Signals Driven by Intel ICH2..................73 5.4.1.3 Topology 2A: INIT#.............. 74 ® 5.4.1.4 Topology 2B: Asynchronous GTL+ Signals Driven by Intel ICH2..................
Page 5 8-Bit Hub Interface Decoupling Guidelines ......... 130 Hub Interface Routing Guidelines - Four-Layer Motherboard ......131 I/O Controller Hub 2 ......................133 ® This Chapter Provides Information on the Intel 82801BA I/O Controller Hub 2 (ICH2) IDE Interface ................... 133 9.1.1 IDE Cable....................
Page 6 Crystals and Oscillators ............. 172 9.9.3.4 Phoneline HPNA Termination..........173 9.9.3.5 Critical Dimensions ............174 9.9.3.5.1 Distance from Magnetics Module to Line RJ11 . 174 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 7 FWH Vpp Design Guidelines .............. 185 ® 9.12 Intel ICH2 Decoupling Recommendations............186 ® 9.13 Glue Chip 4 (Intel ICH2 Glue Chip)..............186 9.14 SPKR Pin Consideration..................187 9.15 1.8 V and 3.3 V Power Sequence Requirement..........188 9.16 PIRQ Routing...................... 189 Additional Design Considerations ...................
Page 8 Processor Keep-Out Zones ..............271 16.1.4 Processor Decoupling................. 272 ® 16.1.5 Intel 82850 MCH Decoupling ............272 16.1.6 AGTL+ ( V HDVREF [3:0], HAVREF [1:0] and CCVREF)....273 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 9 16.10 Intel ICH2 Decoupling ..................287 16.11 RTC ......................288 16.12 LAN* Connect Interface..................288 16.13 Miscellaneous ..................... 289 Appendix A: Reference Schematics ....................... 291 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 10 ® ® Figure 10. 4-Layer Intel Pentium 4 Processor in the 478 Pin Package and Intel Chipset Example Stack-Up for µATX Form Factor............ 38 Figure 11. Clocking Architecture Using the CK00............. 40 Figure 12. Processor BCLK Topology................41 Figure 13. Source Shunt Termination ................42 Figure 14.
Page 11 Figure 70. SIO Routing....................106 Figure 71. Rambus RDRAM* Device CMOS Shunt Transistor........108 Figure 72. Rambus RIMM Connector Placement ............110 ® Figure 73. Rambus Technology Intel MCH Breakout (Top Layer) ........ 111 ® Figure 74. Rambus Technology Intel MCH Breakout (Bottom Layer) ......
Page 12 Figure 113. External Circuitry for the Intel ICH2 RTC ........... 157 Figure 114. Diode Circuit to Connect RTC External Battery ........... 159 ® Figure 115. RTCRST External Circuit for the Intel ICH2 RTC........160 Figure 116. RTC Power-Well Isolation Control ............... 161 ®...
Page 13 Figure 178. Desired Mode of Power Sequencing............235 Figure 179. Optional Mode of Power Sequencing............235 Figure 180. V5REF Sequencing Circuit ................236 Figure 181. CPU/CK00 Sequencing Circuit ..............237 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 14 Table 45. Boxed Processor Fan Power Header Pinout ..........195 Table 46. Decoupling Requirements ................200 Table 47. Decoupling Locations ..................200 Table 48. Four-Phase Decoupling Requirements ............202 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 15 Table 54. Intel Pentium 4 Processor Power Delivery Model Parameters ....224 ® ® Table 55. Intel 850 Chipset and Intel ICH2 Thermal Design Power ......231 ® Table 56. Intel MCH 1.8 V RAC Pinout ................. 232 ® ®...
Page 16 • Revised Section 15.6, Rambus RIMM* Connector Checklist -007 • Added FMB2 design guidelines into Section 11 Jan 2003 • Separated FMB1 and FMB2 design guidelines -008 Jan 2003 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 17: Introduction
® • Intel Pentium 4 processor with 512-KB L2 cache on 0.13 micron process This design guide documents Intel’s design recommendations for systems based on the Pentium 4 ® ® processor in the 478-pin package with the Intel 850 chipset family, which consists of the Intel ®...
Page 18: Related Documentation
Introduction Related Documentation Refer to the following documents or models for more information. All Intel issued documentation revision numbers are subject to change, and the latest revision should be used. The specific revision numbers referenced should be used for all documents not released by Intel.
Page 19: Conventions And Terminology
• Maximum flight time is the largest acceptable flight time a network will experience under all variations of conditions. • Minimum flight time is the smallest acceptable flight time a network will experience under all variations of conditions. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 20 Definition GTL+ GTL+ is the bus technology used by the Intel Pentium Pro processor. This is an incident wave switching, open-drain bus with pull-up resistors that provide both the high logic level and termination. It is an enhancement to the GTL (Gunning Transceiver Logic) bus technology.
Page 21: System Overview
The advanced transfer cache is a 256 KB (512 KB for the Intel Pentium 4 processor with 512-KB L2 cache on 0.13 micron process), on-die level 2 cache with an increased bandwidth over previous micro-architectures. The floating point and multi- media units have been improved by making the registers 128 bits wide and adding a separate register for data movement.
Page 22: Intel 82850/82850E Memory Controller Hub (Mch)
82850/82850E Memory Controller Hub (MCH) The MCH component provides the processor interface, Direct RDRAM device interface, AGP interface and hub interfaces in an Intel 850 chipset platform. The MCH is in a 615-ball OLGA package and has the following functionality: •...
Page 23: System Configurations
Introduction 1.3.3 System Configurations Figure 1 illustrates a typical processor and Intel 850 chipset-based system configuration for professional and high performance desktops using the Pentium 4 processor in the 478-pin package. Figure 1.Typical System Configuration Processor Main Memory ® Intel...
Page 24: Platform Initiatives
AGP is based on a set of performance extensions or enhancements to the PCI bus. The Intel 850 chipset employs an AGP interface that is optimized for a point-to-point topology using 1.5 V signaling in 4x mode. The 4x mode provides a peak bandwidth of 1066 MB/s.
Page 25: Intel ® Ac'97 6-Channel Support
By using an audio codec, the AC-link allows for cost-effective, high-quality, integrated audio on the Intel 850 chipset platform. In addition, an AC’97 soft modem can be implemented with the use of a modem codec. Several system options exist when implementing AC’97. The ICH2 integrated digital link allows two external codecs to be connected to the ICH2 in several configurations.
Page 26: Low Pin Count (Lpc) Interface
— especially during sequential operations. Users of new Intel 850 chipset-based systems will need less time to boot their systems and open applications, a direct result of the improved throughput provided by Ultra ATA. Current disk drive technology has been optimized to perform within the limits of the legacy protocol (16.6 MB/s).
Page 27: Platform Manageability
1.4.3 Platform Manageability The Intel 850 chipset platform integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system and recover from system lockups without the aid of an external micro-controller.
Page 28: Pc '99/'01 Platform Compliance
DVD, scanners and digital cameras, and other devices. Refer to the PC ‘99 System Design Guide and PC ’01 System Design Guide at http://www.pcdesguide.org for additional information. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 29: Component Quadrant Layout
Figure 2. Processor Socket Quadrant Layout Data Clocks Vcc/Vss Processor Common Clock Address =Power Pin 1 in this corner =GND =Signal Quad_Lay_Processor ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 30: Intel ® 850/850E Chipset Component Quadrant Layout
Component Quadrant Layout ® Intel 850/850E Chipset Component Quadrant Layout Figure 3 and Figure 4 show the quadrant layouts for the Intel 850 chipset components. ® Figure 3. Intel 850/850E Chipset Quadrant Layout OLGA RAC A Interface Pin 1 in this corner ®...
Page 31: Platform Placement And Stack-Up Overview
3.1.1 Six-Layer Motherboard Figure 5 shows general component placement for a Pentium 4 processor in the 478-pin package and Intel 850 chipset-based desktop 6-layer motherboard system. The assumptions used for the component placement are described in Table 3 and are consistent with the 6-layer customer reference board (CRB) schematics.
Page 32: Four-Layer Motherboard
3.1.2 Four-Layer Motherboard Figure 6 shows general component placement for a Pentium 4 processor in the 478-pin package and Intel 850 chipset-based desktop 4-layer motherboard system. The assumptions used for the component placement are described in Table 3 and are consistent with the 4-layer customer reference board (CRB) schematics.
Page 33: Figure 6. Desktop Component Placement Example (4-Layer Motherboard)
Platform Placement and Stack-Up Overview Figure 6. Desktop Component Placement Example (4-Layer Motherboard) Socket- RIMM Connector, RIMM Connector, Floppy ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 34: Four-Layer Motherboard Routing Strategy
 Half of the system bus signals are routed on the top layer referenced to V and the other half of the signals are routed on the bottom layer referenced to GND. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 35: Figure 7. Four-Layer Routing Strategy
PCI Bus Socket-478 System Bus System Bus RAC B RIMM Connector, Channel A RIMM Connector, Channel A Hub Interface IDE Connector IDE Connector Floppy Connector ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 36: Motherboard Layer Stack-Up
Figure 8. Six Layer Stack-Up 6 Layers Layer 0 Signal Vcc Plane Layer 1 Layer 2 Signal Layer 3 Signal Vss Plane Layer 4 Layer 5 Signal 6-Layer_stackup ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 37: Design Considerations
(unplated 1oz Cu) L5 - G round 1.2 m ils (unplated 1oz C u) Bot - Signal 2.1 m ils (plated 1/2oz C u) Total 61.6 Stack_ATX_850-P4 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 38: Four-Layer Motherboard Stack-Up
4.5 Mil Prepreg Solder Side Layer 4 ½ oz cu Design Considerations Intel has found that the following recommendations aid in the design of an Intel Pentium 4 processor-based platform. • Impedance requirements  60-ohm impedance ± 15% for AGP at 5mil trace width ...
Page 39: Platform Clock Routing Guidelines
Synthesizer/Driver Design Guidelines. , For the 82850E chipset with 533 MHz processor system bus, refer to the CK00-E Clock Synthesizer/Driver Design Guidelines, for Intel® Pentium® 4 Processor in the 478 pin Package / Intel® 850-E Chipset Platform with 533 MHz Processor System Bus. The CK00 Clock Synthesizer/Driver Design Guidelines and CK00-E Clock Synthesizer/Driver Design Guidelines specify the platform clocking solution that can be used in the processor and Intel 850 chipset-based design - the CK00 or CK00-E clock synthesizer.
Page 40: Figure 11. Clocking Architecture Using The Ck00
14.318 MHz CLK14 Connectors 33 MHz 33 MHz 33 MHz 14.318 MHz REFO CLOCKI 33 MHz PCI_CLK Glue Chip 33 MHz CLK_IN 33 MHz Clk_Arch_Ck00 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 41: Routing Guidelines For System Bus Clocks
CK00 to a voltage and matching the driver output impedance to the transmission line. The series resistors Rs provide isolation from the ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 42: Figure 13. Source Shunt Termination
• Vias placed in one half of a differential pair must be matched by a via in the other half. Differential vias can be placed within length L1, between clock driver and RS, if needed to shorten length L1. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 43: Table 5. Bclk [1:0] Routing Guidelines
0 – 0.2 inches Figure 13 L3: RS-RT node to Rt MCH routing length – 0 – 12 inches Figure 13 L4, L4': RS-RT Node to Load ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 44 11. Rt shunt termination value should match the system board impedance. 12. Minimize L1, L2 and L3 lengths. Long lengths on L2 and L3 degrade effectiveness of source termination and contribute to ring back. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 45: Figure 14. Clock Skew As Measured From Agent To Agent
Platform Clock Routing Guidelines Figure 14. Clock Skew as Measured from Agent to Agent Figure 15. Trace Spacing Trace_Space ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 46: Bclk[1:0] Frequency Select
BCLK[1:0] Frequency Select ® 4.2.1 100 MHz Operation – Intel 82850 Chipset The BCLK[1:0] frequency should be set for 100 MHz operation for the 82850 chipset. This is accomplished with a 470 Ω pull-down on the CK-00 SEL100/133 input. In addition, the platform should be prevented from operating with a processor that requires a BCLK[1:0] frequency other than 100 MHz.
Page 47: 133 Mhz Operation - Intel 82850E Chipset
Platform Clock Routing Guidelines ® 4.2.2 133 MHz Operation – Intel 82850E Chipset The BCLK[1:0] frequency should be set for 133 MHz operation for the 82850E chipset. This is accomplished with a 1 kΩ pull-up to VCC3_CLK on the CK-00 SEL100/133 input. The correct frequency select circuitry is show in the Figure below.
Page 48: Routing Guidelines For Rambus Rdram* Device Clocks
6 m ils 6 m ils 6 m ils 4.5 m ils Ground/Power Plane VddIR_3VMRef_route NOTE: 3VMRef# should be routed in a similar manner as 3VMRef. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 49: Intel ® Mch To Rambus Drcg* (Phase Aligning Clocks)
NOTE: The signals Rclkout and Pclkout are channel specific, and their exact names are CHx_RCLKOUT and ® CHx_PCLKOUT, where x is the channel, either A or B. Consult the Intel 850 Chipset Family: 82850/82850E Memory Controller Hub (MCH) Datasheet t for more information.
Page 50: Trace Lengths
CFM/CFM#) be routed differentially. An example recommended topology for microstrip differential clock routing is shown in Figure 21. Note: Clock trace widths and spacing may change with different prepreg thicknesses. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 51: Figure 21. Differential Clock Routing
The 10 mil ground isolation traces must be connected to ground with a via per every 1 inch. A 6 mil gap is required between the clock signals and the ground isolation traces. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 52: Topology Considerations
533 MHz RDRAM technology: The CFM/CFM# differential pair signals require termination using 27 Ω 1% resistors and a 0.1 µF capacitor as shown in Figure 24. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 53: Figure 23. Cfm/Cfm# Termination - 300/400 Mhz Rambus Rdram* Technology
Ω - 1% CFM_Term Figure 24. CFM/CFM# Termination – 533 MHz Rambus RDRAM* Technology 27 Ω - 1% 0.1 uF 27 Ω - 1% CFM_Term_533 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 54: Rambus Drcg* Impedance Matching Circuit
5. Cmid at 0.1 µF has improved jitter versus Cmid at 100 pF. However, this will increase the latency coming out of a stop clock or tri-state mode. 6. RS, RP, RT were modified to improve channel signal integrity through increasing CTM/CTMN swing. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 55: Rambus Drcg* Layout Example
(Place VERY Near DRCG 3.3V Pin!) (Place VERY Near DRCG 3.3V Pin!) Bulk Decoupling Cap - 10uF (Place Near DRCG) Ferrite Bead (L22 in Reference Schematics) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 56: Routing Guidelines For 66 Mhz And 33 Mhz Clocks
Table 8 summarizes the layout recommendations between the CK00 clock synthesizer and the AGP connector, MCH and ICH2 components, which require a 66 MHz clock. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 57: 66 Mhz Clock Routing Length Guidelines
Figure 29. CLK_66 Clock Routing Topology CK00 Clock Synthesizer ICH2 Clk_Routing_CLK-66 ® 4.4.2.1 3V66 Clock Routing Requirement for Intel 82850E Platforms The 3V66 trace (CK_G_66M_MCH) from the Clock Chip to MCH cannot be shorter than the CPU Clock trace (CK_H_100M_MCH, CK_H_100M_MCH). ® ® ® Intel...
Page 58: 33 Mhz Clock Routing Length Guidelines
Figure 30 and Figure 31 show the recommended clock routing topologies for the 33 MHz clocks. Figure 30. PCI_33 Clock Routing Topology CK00 Clock Synthesizer Clk_Routing_PCI-33 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 59: Figure 31. Clk_33 Clock Routing Topology
Platform Clock Routing Guidelines Figure 31. CLK_33 Clock Routing Topology ICH2 CK00 Clock Synthesizer Clk_Routing_CLK-33 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 60 Platform Clock Routing Guidelines This page is intentionally left blank. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 61: System Bus Routing
A layer transition may occur if the reference plane remains the same (VSS) and the layers are all of the same configuration (all stripline or all microstrip). ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 62: Return Path
• Do not allow routing of signals on the reference planes near system bus signals. • Maintain VSS as a reference plane for all system bus signals. • Do not route over via anti-pads or socket anti-pads. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 63: Gtlref Layout And Routing Recommendations
Do not allow signal lines to use the GTLREF routing as part of their return path (i.e., do not allow the GTLREF routing to create splits or discontinuities in the reference planes of the system bus signals.) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 64: Processor Configuration
Processor Configuration Both recommendations and considerations are described in this section. For proper operation of the processor and the Intel 850 chipset, it is necessary that the system designer meet the timing and voltage specifications of each component. The following recommendations are Intel’s best guidelines based on extensive simulation and experimentation...
Page 65: Design Recommendations
A strobe and its complement (xSTBp/n#) should be routed to ±25 mils of the same length. It is recommended to simulate skew in order to determine the length that best centers the strobe for a given system. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 66: Design Considerations
850 MCH Package trace Motherboard PCB trace 5.3.1.2 Design Considerations Intel has found that the following recommendations aid in the routing of the processor, given the example stack-up shown in Figure 9. • Line width is 7.0 mil. • Trace to trace spacing is 13.0 mil (except in component breakout where spacing is constrained where 5 mil spacing is acceptable) Table 12.
Page 67 0.365 DSTBP#[0] 0.291 0.362 D#[00] 0.393 0.434 D#[01] 0.456 0.494 D#[02] 0.517 0.559 D#[03] 0.583 0.634 D#[04] 0.365 0.407 D#[05] 0.360 0.411 D#[06] 0.505 0.565 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 68 0.254 D#[29] 0.391 0.410 D#[30] 0.303 0.323 D#[31] 0.467 0.479 DBI#[1] 0.455 0.460 Data Group 2 DSTBN#[2] 0.250 0.254 DSTBP#[2] 0.268 0.265 D#[32] 0.310 0.291 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 69 0.457 D#[56] 0.447 0.460 D#[57] 0.423 0.430 D#[58] 0.333 0.339 D#[59] 0.385 0.386 D#[60] 0.230 0.214 D#[61] 0.431 0.422 D#[62] 0.269 0.268 D#[63] 0.400 0.387 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 70 4 Processor with 478-pin Package Length (inches) 512-KB L2 Cache on 0.13 Micron Process Package Length (inches) DBI#[3] 0.203 0.201 BCLK BCLK[0] 0.540 0.596 BCLK[1] 0.539 0.598 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 71: Routing Guidelines For Asynchronous Gtl+ And Other Signals
2. All miscellaneous signals that require a pull up should be pulled up to VCC_CPU. All signals must meet the AC and DC specifications as documented in the processor datasheet. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 72: Topologies
Table 14. Layout Recommendations for FERR# Signals (Topology 1a) Trace Zo Trace Spacing 60 Ω 7 mil 1–12” 3” max 62 ±5% Ω Figure 34. Routing Illustration for FERR# VCC_CPU Processor ICH2 Topo1_FERR_Route ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 73: Topology 2: Asynchronous Gtl+ Signals Driven By Intel
VDD CPU Topo1b_PROCHOT_Route ® 5.4.1.2 Topology 2: Asynchronous GTL+ Signals Driven by Intel ICH2 These signals (A20M#, IGNNE#, LINT[1:0], SLP#, SMI#, and STPCLK#) should adhere to the following routing and layout recommendations. Figure 36 illustrates the recommended topology. Table 16. Layout Recommendations for Miscellaneous Signals (Topology 2)
Page 74: Topology 2A: Init
Level shifting is required for the INIT# signal to the FWH in order to meet the input logic levels of the FWH. Figure 38 illustrates one method of implementing this level shifting. Figure 38. Voltage Translation of INIT# 4.7k INIT# from 4.7k ICH2 Volt_Trans_INIT ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 75: Topology 2B: Asynchronous Gtl+ Signals Driven By Intel
System Bus Routing ® 5.4.1.4 Topology 2B: Asynchronous GTL+ Signals Driven by Intel ICH2 This signal (Open Drain; PWRGOOD) should adhere to the following routing and layout recommendations. Figure 39 illustrates the recommended topology. Table 18. Layout Recommendations for Miscellaneous Signals (Topology 2B)
Page 76: Topology 4: Br0# And Reset
Connect the signals between the components as shown in Figure 41. The Intel 850 chipset has on-die termination and thus it is necessary to terminate only at the processor end. The value of Rt should be 51 Ω ±5% for RESET#.
Page 77: Topology 7: Thermda/Thermdc Routing Guidelines
In the case of the ITPCLKOUT[1:0], directly tying to VCC is strongly discouraged for system boards that do not implement an onboard debug port. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 78: Topology 9: Processor Voltage Regulator Sequencing Requirements
Topology 9: Processor Voltage Regulator Sequencing Requirements The Pentium 4 processor with 512KB L2 cache on .13 micron process requires a 1.2 V supply to the VCCVID pin to support the on-die VID generation circuitry. The current requirements for this voltage is 30 mA.
Page 79: Figure 42. Passing Monotonic Rising Edge Voltage Waveform
System Bus Routing Figure 42. Passing Monotonic Rising Edge Voltage Waveform Figure 43. Failing Non-monotonic Rising Voltage Waveform ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 80: Topology 10: Thermtrip# Power Down Circuit
VID[4:0] Processor Voltage Processor Regulator VID_Good *VID_Good connected to voltage Generation regulator controller output enable delay Logic System Power VCCVID Voltage PS_PWR_OK Supply Regulator Power_Sequencing ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 81: Figure 46: Power-On Sequence Timing Diagram
2. When VCCVID is less than 1V, VID_GOOD must be low. 3. Vcc must be disabled before VID[4:0] becomes invalid. Power-off_Sequence_Timing ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 82: Intel ® Mch System Bus Interface
1. The MCH has only one dedicated voltage divider. 2. Decouple the voltage divider with a 1 µF capacitor. 3. Keep the voltage divider within 1.5 inches of the MCH Vref ball ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 83: Intel ® Mch System Bus I/O Decoupling Requirements
• 2 minimum, 3 preferred 0.1 µF capacitors with 603 packages distributed evenly over the System Bus address and control lines • All capacitors placed as close as possible to the MCH package (within 150 mils) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 84: Figure 51. Example Intel ® Mch Decoupling Guidelines For Chipset
System Bus Routing ® Figure 51. Example Intel MCH Decoupling Guidelines for Chipset Address and 2-3 0.1 uF with 603 body Control Field over the address and control signals and as close to the chipset package as possible 4-5 0.1 uF with 603 body...
Page 85: System Bus Routing Guidelines - Four-Layer Motherboard
The following are descriptions and illustrations of system bus routing on the 4-layer customer reference board. Figure 52. Customer Reference Platform System Bus Routing – Top Layer Top Layer Addr Data ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 86: Figure 53, Customer Reference Platform System Bus Routing - Bottom Layer
GND flood is continuous from the OSCONs to the high frequency ceramic capacitors to help minimize the inductance of the power and ground planes. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 87: Processor Power Delivery
The voltage island from the source of power to the load should not have any breaks, so as to minimize inductance in the plane. Also, it should completely surround all of the pins of the power source and all of the pins in the power pin area of the Pentium 4 processor in the 478-pin package. ®...
Page 88: Figure 55. Processor Power Delivery On Layer 4
System Bus Routing Figure 55. Processor Power Delivery on Layer 4 Layer 4 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 89: Memory Interface Routing
(including the MCH) running at 800 MegaTransfers/second (MT/s). The following sections will document the design guidelines to help ensure a robust Direct Rambus channel design. Refer http://www.rambus.com/html/direct_docs.html for more information regarding RDRAM technology. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 90: Rambus Rdram* Device Routing Guidelines
The signals on the Direct Rambus channel are broken into three groups: Rambus Signaling Level (RSL) signals, CMOS signals and clocking signals. The signal groups are documented in Table 21. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 91: Rambus Signaling Level (Rsl) Signals
For example, a prepreg thickness of 4.0 to 4.5 mils allows 18 mil wide traces to meet the 28 Ω ± 10% nominal impedance requirement. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 92: Figure 57. Example Direct Rambus Channel Routing
2. For MCH to first RIMM connector measurement, use CFM/CFM# (CTM/CTM# use a different trace length calculation based on the formulas specified in Section 6.1.2.3) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 93: Figure 58. Rsl Routing Diagram Showing Ground Isolation Traces With Via Around Rsl Signals
10 mils Gound Isolation Trace NOTE: For the Intel 850 chipset customer reference board (CRB), both inner and outer layer RSL trace width is 18 mils. Inner layer RSL trace width may vary depending on the board stack-up used. RSL signals should be no wider than 18 mils to prevent neck-down in the RIMM connector pin field.
Page 94: Rambus* Signaling Level (Rsl) Channel Compensation
Figure 59. Direct Rambus Channel Trace Length Matching Example Package NOTE: This diagram only illustrates the routing of one Direct Rambus channel. However, the example routing shown can be applied to both channels. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 95: Via Compensation
• Stripline velocity typically equals 172 ps/in • Microstrip velocity typically equals 154 ps/in ® The MCH package trace length information is contained in the Intel 850 Chipset: 82850 Memory Controller Hub (MCH) Datasheet. The package trace length information presented in this document is normalized to the longest package trace length.
Page 96: Differential Clock Compensation
CFM/CFM# Clock Length = Nominal RSL Signal Length (package + board)* 1.030 CTM/CTM# Clock Length = Nominal RSL Signal Length (package + board)* 1.030 + 45 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 97: Non-Differentially Routed Clocks - 533 Mhz Rambus Rdram* Technology
Memory Interface Routing Note: This compensation factor is based on the Intel 850 chipset customer reference board (CRB) stack- The lengthening of the clock signals, to compensate for their trace velocity change, only applies to routing between the MCH and first RIMM connector. The clock signals should be matched in length to the RSL signals between RIMM connectors.
Page 98: Signal Layer Alternation For Rambus Rimm Connector Pin Compensation
• LCFM# • • LCTM# RROW[2:0] LDQA[8:0] • • RCFM • • RCTM LCOL[4:0] RDQB[8:0] • • RCFM# • • RCTM# RCOL[4:0] LDQB[8:0] • • SCK ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 99: Table 23. Rsl And Clocking Signal Rambus Rimm* Connector Capacitance Requirement
• Thickness of prepreg = Stack-up dependent • Length, Width = Dimensions in mils of copper plate to be added • Factor of 1.1 accounts for fringe capacitance. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 100: Figure 62. Top Layer Ctab With Rsl Signal Routed On The Same Layer (Ceff = 0.8
Figure 62. Top Layer CTAB with RSL Signal Routed on the Same Layer (Ceff = 0.8 pF) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 101: Figure 63. Bottom Layer Ctab With Rsl Signal Routed On The Same Layer
Figure 64 issues the use of CTABs on the top and bottom layer for bottom layer RSL and clocking signals routed between RIMM connectors. Figure 64. Bottom Layer CTABs Split Across the Top and Bottom Layer to Achieve an Effect Ceff ~1.35 pF ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 102: Rsl Signal Termination
Vterm power island should be AT LEAST 50 mils wide. This voltage is not required during Suspend-to-RAM (STR). Figure 65. Direct Rambus RDRAM* Device Termination (Discrete Resistors Are Recommended) Termination Resistors Signals Vterm ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 103: Figure 66. Direct Rambus Rdram* Device Termination Example
Memory Interface Routing Figure 66. Direct Rambus RDRAM* Device Termination Example ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 104: Rambus Rdram* Device Reference Voltage
NOTE: The RAMREF Generation Circuit is not shown for Channel A in Figure 68, but is the same as the one shown for Channel B. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 105: High-Speed Cmos Routing
10 kΩ terminating resistor is required on the last RIMM connector’s SOUT pin. This resistor needs to be tied to GND. The SIO is routed with a 5 mil wide, 60 Ω trace. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 106: Figure 70. Sio Routing
Memory Interface Routing Figure 70. SIO Routing RIMM #1 RIMM #2 SOUT SOUT 2.2K - 10K ohm ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 107: Suspend-To-Ram Shunt Transistor
CMD and SCK must have a neck down from 18 mil traces to 5 mil traces for 175 mils on either side of the SCK/CMD attach point as shown in Figure ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 108: Rambus Rdram* Device Channel Margin Improvement
6.1.8 Rambus RDRAM* Device Channel Margin Improvement For Intel 850E / 533 MHz (PC1066) RDRAM device designs which exhibit less than optimum Rambus channel margins, margin improvement may be achieved by: • Increasing the number of bypass capacitors from one 0.1µF ceramic chips capacitors per two RSL lines to two 0.1µF ceramic chip capacitors per two RSL lines.
Page 109: 533 Mhz (Pc1066) Rambus Rimm Module Thermal Consideration
533 MHz (PC1066) RIMM modules will generate more heat than 400 MHz (PC800) RIMM modules. System designers should insure proper airflow to prevent overheating of memory or other components in the system environment when using PC1066 RIMM modules. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 110: Rambus Technology Routing Guidelines - Four-Layer Motherboard
To enable a 4-layer design, the RIMM connectors on channel A are placed horizontal and form a 90 degree angle to the RIMM connectors on channel B. See figure below for placement information. Figure 72. Rambus RIMM Connector Placement ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 111: Figure 73. Rambus Technology Intel
RSL signals around the hub interface need to be routed on the top layer to maximize the 1.8V core and RAC power delivery. Follow the MCH Rambus technology breakout shown in the following figures. ® Figure 73. Rambus Technology Intel MCH Breakout (Top Layer) Top Layer Channel B Channel A ®...
Page 112: Optimized Rambus Rdram* Device Routing Rules For A Four-Layer Motherboard Design
® ® ® in the Intel Pentium 4 Processor in the 478 Pin Package / Intel 850 Chipset Family Platform Design Guide. General optimized routing guidelines that apply to Channel A and Channel B • Do NOT implement dummy VIAs on RSL signals routed on the top layer.
Page 113: Agp Interface Routing
Specification, Revision 1.0 by allowing 4x data transfers and 1.5 V operation. In addition to these enhancements, additional performance enhancement and clarifications, such as fast write capability, are included in the AGP Interface Specification, Revision 2.0. The Intel 850 chipset supports these enhanced features and 1.5 V signaling only.
Page 114: Agp Routing Guidelines
AD_STB1#, and SBA[7:0] is associated with SB_STB and SB_STB#. AGP Routing Guidelines The following section documents the recommended routing guidelines for Intel 850 chipset-based designs. All aspects of the interface will be covered from signal trace length to decoupling. These trace length guidelines apply to ALL of the signals listed as 2X/4X timing domain signals.
Page 115: Trace Lengths Greater Than 6 Inches And Less Than 7.25 Inches
20 mils (1:4). The strobe pair must be length matched to less than ±0.1 inches (that is, a strobe and its compliment must be the same length within 0.1 inches). ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 116: Agp Interfaces Trace Length Summary
2. Each strobe pair must be the same length. 3. These guidelines apply to board stack-ups with 10% impedance tolerance. 4. These guidelines apply to board stack-ups with 15% impedance tolerance ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 117: I/O Decoupling Guidelines
The designer should ensure that the AGP connector is well decoupled as described in the revision 1.0 of the AGP Design Guide, Section 1.5.3.3. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 118: Signal Power/Ground Referencing Recommendations
AGP specifies two separate power planes: VCC and VDDQ. VCC is the core power for the graphics controller and is always 3.3 V. VDDQ is the interface voltage. The Intel 850 chipset only supports an interface voltage of 1.5 V.
Page 119: Mch Agp Interface Buffer Compensation
RSTIN# assertion. The recommended value is the same as the other AGP common clock signals. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 120: Table 27. Agp Pull-Up/Pull-Down Resistors
3.3 V 2x/4x Timing Domain AD_STB[1:0] pull-up resistor to VDDQ SB_STB pull-up resistor to VDDQ AD_STB[1:0]# pull-down resistor to GND SB_STB# pull-down resistor to GND ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 121: Agp Signal Voltage Tolerance List
AGP Universal Retention Mechanism (RM) Environmental testing and field reports indicate that AGP cards may come unseated during system shipping and handling without proper retention. In order to avoid disengaged AGP cards, Intel recommends that AGP based platforms use the AGP retention mechanism (RM).
Page 122: Figure 78. Agp Left Handed Retention Mechanism Drawing
The additional notch feature in the mechanical keying tab is required for 1.5-volt AGP cards and is recommended for the new 3.3-volt AGP cards. Figure 78. AGP Left Handed Retention Mechanism Drawing ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 123: Figure 79. Agp Left Handed Retention Mechanism Keep-Out Information
Graphics Port (AGP) Interface Specification, Revision 2.0. Intel intends to incorporate the AGP RM changes into later revisions of the AGP Interface Specification. In addition, Intel has defined a reference design of a mechanical device to utilize the features defined in ECR #48.
Page 124: Agp Routing Guidelines - Four-Layer Motherboard
AGP signals are routed on the bottom of the board reference GND. Signals routed on the top of the board are referenced to V Figure 80. Example AGP Routing (Top Layer) Top Layer ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 125: Figure 81. Example Agp Routing (Bottom Layer)
AGP Interface Routing Figure 81. Example AGP Routing (Bottom Layer) Bottom Layer ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 126: Figure 82. Example Vddq Plane On Layer 2
AGP Interface Routing Figure 82. Example VDDQ Plane on Layer 2 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 127: Hub Interface Routing
(HL_STB). For the 8-bit hub interface, HL[0:7] are associated with HL_STB and HL_STB#. Figure 83. 8-Bit Hub Interface Routing Example HL_STB HL_STB# ICH2 HL[11:0] CLK66 CLK66 Clock Synthesizer hub_route_8bit ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 128: 8-Bit Hub Interface Routing Guidelines
ICH2. If the single HIREF divider is located more than 3.5 inches away, then the locally generated hub interface reference dividers should be used instead. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 129: Figure 84. 8-Bit Hub Interface With A Shared Reference Divider Circuit (Normal Mode)
(C2 in the above circuits) should be placed within 0.25 inches of each HUBREF pin. The trace length from the divider circuit to the HLREF pin must be no longer than 3.5 inches. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 130: 8-Bit Hub Interface Compensation
Similarly, if layout allows, metal fingers running on the VCC1_8 side of the board should connect the ground side of the capacitors to the VSS power pins. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 131: Hub Interface Routing Guidelines - Four-Layer Motherboard
2 and 4 as well as attach to the high reference decoupling capacitors. See the below graphic for more details. Figure 86. Example Hub Interface Breakout / 1.8 V MCH Fingers MCH Top Layer ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 132 Hub Interface Routing This page is intentionally left blank. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 133: I/O Controller Hub 2
I/O Controller Hub 2 I/O Controller Hub 2 ® This Chapter Provides Information on the Intel 82801BA I/O Controller Hub 2 (ICH2) IDE Interface This section contains guidelines for connecting and routing the ICH2 IDE interface. The ICH2 has two independent IDE channels. This section provides guidelines for IDE connector cabling and system board design, including component and resistor placement, and signal termination for both IDE channels.
Page 134: Cable Detection For Ultra Ata/66 And Ultra Ata/100
IDE device. If a 40-conductor cable is detected, the system software must not enable modes faster than Ultra DMA Mode 2 (Ultra ATA/33). Intel recommends that cable detection be done using a combination Host-Side/Device-Side detection mechanism. Note that Host-Side detection cannot be implemented on an NLX form factor system, since this configuration does not define interconnect pins for the PDIAG#/CBLID# from the riser (containing the ATA connectors) to the motherboard.
Page 135: Combination Host-Side/Device-Side Cable Detection
(Device 1) is preventing proper cable detection, and BIOS should configure the system as though a 40-conductor cable is present, and notify the user of the problem. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 136: Device-Side Cable Detection
The drive can detect the difference in rise times and it will report the cable type to the BIOS when it sends the IDENTIFY_DEVICE packet during system boot as described in the ATA/66 specification. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 137: Primary Ide Connector Requirements
• Series resistors can be placed on the control and data line to improve signal quality. The resistors are place as close to the connector as possible. Values are determined for each unique motherboard design. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 138: Secondary Ide Connector Requirements
• Series resistors can be placed on the control and data line to improve signal quality. The resistors are place as close to the connector as possible. Values are determined for each unique motherboard design. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 139: Communication And Networking Riser (Cnr)
Power and 1 PLC device) Reserved CNR Connector CNR_interface 9.2.1 CNR Placement Refer to the Communication and Network Riser Specification, Revision 1.0 for CNR placement. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 140: Intel ® Ac'97
The ICH2 implements an AC’97 2.1 compliant digital controller. Any codec attached to the ICH2 AC-link must be AC’97 2.1 compliant as well. Contact your codec vendor for information on 2.1 compliant products. The AC’97 2.1 specification is on the Intel website: http://developer.intel.com/pc-supp/platform/ac97/index.htm The AC-link is a bi-directional, serial PCM digital stream.
Page 141: Figure 93. Audio Codec
AC’97 Link ICH2 Audio / Modem Codec AC97_M_codecs Figure 95. Audio/Modem Codec Modem Port AC’97 Digital AC’97 Link ICH2 Audio/ Modem Codec Audio Port AC97_A-M_codec ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 142: Figure 96. Modem Codecs
Codec AC97_2-M_codecs Figure 97. Audio and Modem Codecs M odem Port AC’97 M odem Codec AC’97 Digital Link ICH2 AC’97 Audio/ Codec Audio Port AC97_A-and-M_codecs ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 143: Figure 98. Audio Codecs
= 60 Ω ± 15% AC-link. Trace impedance should be Z Intel has developed an advanced common connector for both AC’97 as well as networking options. This is known as the Communication Network Riser (CNR). Clocking is provided from the primary codec on the link via BITCLK, and is derived from a 24.576 MHz crystal or oscillator.
Page 144: Ac'97 Audio Codec Detect Circuit And Configuration Options
Options The following provides general circuits to implement a number of different codec configurations. Refer to Intel’s White Paper Recommendations for ICHx/AC’97 Audio (Motherboard and Communication and Network Riser) for Intel’s recommended codec configurations. To support more than two channels of audio output, the ICH2 allows for a configuration where two audio codecs work concurrently to provide surround capabilities.
Page 145: Figure 100. Cdc_Dn_Enab# Support Circuitry For A Single Codec Motherboard
Both Figure 101 and Figure 102 show a switch on the CNR board. This is necessary to connect the CNR board codec to the proper SDATA_INn line as to not conflict with the motherboard codec(s). ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 146: Figure 101. Cdc_Dn_Enab# Support Circuitry For Multi-Channel Audio Upgrade
Figure 103 shows the case of two-codecs down and a dual-codec CNR. In this case, both codecs on the motherboard are disabled (while both on CNR are active) by R being 10 kΩ and R being 1 kΩ. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 147: Figure 103. Cdc_Dn_Enab# Support For Two-Codecs On Motherboard / Two-Codecs On Cnr
Reset signal from the AC ’97 Digital Controller (ICH2). SDATA_INn AC ’97 serial data from an AC ’97-compliant codec to an AC ’97-compliant controller (i.e., the ICH2). ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 148: Valid Codec Configurations
The P+/P- signal traces must also be the same length. This will minimize the effect of common mode current on EMI. Lastly, do not route over plane splits. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 149: Ioapic Design Recommendations
System Bus interrupt delivery mechanism. • On the ICH2  Tie PICCLK directly to ground  Tie PICD0, PICD1 to ground via 1 k Ω to 10 kΩ resistor ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 150: Smbus/Smlink Interface
SM Bus SM BCLK Microcontroller SM BDATA ICH2 SM Link SMLink0 SMLink1 W ire O R 82850 (optional) M otherboard LAN controller SMbus-SMlink_IF ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 151: Smbus Architecture And Design Considerations
I/O Controller Hub 2 Note: Intel does not support external access of the ICH2’s Integrated LAN Controller via the SMLink interface. Also, Intel does not support access of the ICH2’s SMBus Slave Interface by the ICH2’s SMBUS Host Controller. ®...
Page 152: The Unified Vcc_ Suspend Architecture
2. In suspended modes where VCC_Core is OFF and VCC_Suspend is on, the VCC_Core node will be very near ground. In this case the input leakage of the ICH2 will be approximately 10 uA. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 153: Mixed Architecture
In addition, the ICH2 supports two PC/PCI REQ#/GNT# pairs, one of which is multiplexed with a PCI REQ#/GNT# pair. Figure 109. PCI Bus Layout Example ICH2 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 154: Pci Routing - Four-Layer Motherboard
VCC3.3. Minimize the number of PCI signals that cross power splits. Figure 110. Example PCI Power Planes on Layer 2 Vcc3 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 155: Figure 111. Example Pci Routing On Layer 1
I/O Controller Hub 2 Figure 111. Example PCI Routing on Layer 1 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 156: Figure 112. Example Pci Routing On Layer 4
I/O Controller Hub 2 Figure 112. Example PCI Routing on Layer 4 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 157: Rtc
The ICH2 RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 pins. Figure 113 shows the external circuitry that comprises the oscillator of the ICH2 RTC. ® Figure 113. External Circuitry for the Intel ICH2 RTC VCC3_3SBY VCCRTC Ω...
Page 158: External Capacitors
The voltage of the battery can affect the RTC accuracy. In general, when the battery voltage decays, the RTC accuracy also decreases. High accuracy can be obtained when the RTC voltage is in the range of 3.0v to 3.3v. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 159: Rtc External Rtcrst Circuit
Figure 115 is an example of this circuitry that is used in conjunction with the external diode circuit. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 160: Rtc Routing Guidelines
• Excess noise on VBIAS can cause the ICH2 internal oscillator to misbehave or even stop completely. • To minimize noise of VBIAS It is necessary to implement the routing guidelines described ® above and the required external RTC circuitry as described in the Intel 82801BA I/O ® Controller Hub 2 (ICH2) and Intel 82801BAM I/O Controller Hub 2 Mobile (ICH2-M) Datasheet.
Page 161: Power-Well Isolation Control
Figure 116. RTC Power-Well Isolation Control empty MMBT3906 iP/N 101421-602 RSMRST# RSMRST# from Glue or other source BAV99 iP/N 305901-001 BAV99 iP/N 305901-001 2.2k empty RTC_PWR-Well_Isolation_Cntl ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 162: Power Supply Ps_On Consideration
1Mb HomePNA* LAN 1Mb HomePNA* connection Intel developed a dual footprint for 82562ET and 82562EH to minimize the required number of board builds. A single layout with the specified dual footprint will allow the OEM to install the appropriate LAN connect component to meet the market need. Design guidelines are provided for each required interface and connection.
Page 163: Figure 117. Intel ® Ich2 / Lan Connect Section
General Routing Guidelines B,C,D 9.9.2 General LAN Routing Guidelines and Considerations 82562EH 9.9.3 Intel® 82562EH Home/PNA* Guidelines 82562ET /82562EM 9.9.4 Intel® 82562ET / 82562EM Guidelines Dual Layout Footprint 9.9.6 82562ET / 82562EH Dual Footprint Guidelines ® ® ® Intel Pentium...
Page 164: Intel ® Ich2 - Lan Interconnect Guidelines
The following are guidelines for a single solution motherboard. Either 82562EH, 82562ET, or CNR are installed. Figure 118. Single Solution Interconnect LAN_CLK LAN_RSTSYNC Platform LAN ICH2 Connect LAN_RXD[2:0] (PLC) LAN_TXD[2:0] LAN_single_sol_interconn ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 165: Lom/Cnr Interconnect
— — 82562ET/EH 0.5 to 6.5 — 2.5 to 9 – A 0.5 to 3 Card NOTES: Total trace length should not exceed 13 inches. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 166: Signal Routing And Layout
The motherboard impedances should be controlled to minimize the impact of any mismatch between the motherboard and the add-in card. An impedance of 60 Ω ±15% is strongly recommended; otherwise, signal integrity requirements may be violated. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 167: Line Termination
And as a general rule, place traces from clocks and drives at a minimum distance from apertures by a distance that is greater than the largest aperture dimension. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 168: Trace Geometry And Length
EMI from other signals. • Avoid routing high-speed LAN or Phoneline traces near other high-frequency signals associated with a video controller, cache controller, processor, or other similar devices. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 169: Power And Ground Connections
Good grounding requires minimizing inductance levels in the interconnections and keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly reduce EMI radiation. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 170: Common Physical Layout Issues
(failing FCC) and can cause poor transmit BER on long cables. At a minimum, other signals should be kept 0.3 inches from the differential traces. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 171 Close should be considered to be less than 0.030 inches between the two traces within a differential pair. 0.008 inch to 0.012 inch trace-to-trace spacing is recommended. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 172: Intel ® 82562Eh Home/Pna* Guidelines
For a noise free and stable operation, place the crystal and associated discretes as close as possible to 82562EH, keeping the length as short as possible and do not route any noisy signals in this area. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 173: Phoneline Hpna Termination
1.1 MHz. Refer to the HomePNA* website: www.homepna.org for up-to-date information and recommendations regarding the use of this low-pass filter to meet HomePNA* certifications. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 174: Critical Dimensions
The reflections of a signal may have a high-frequency component that may contribute more EMI than the original signal itself. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 175: Distance From Lpf To Phone Rj11
Ethernet LAN circuits need to be as close as possible to the connector. Thus, it is imperative that all designs be optimized to fit in a very small space. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 176: Crystals And Oscillators
There are two dimensions to consider during layout. Distance ‘B’ from the line RJ45 connector to the magnetics module and distance ‘A’ from the 82562ET or 82562EM to the magnetics module (See Figure 126). ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 177: Distance From Magnetics Module To Rj45
OEMs should verify actual trace impedance and adjust their layout accordingly. If the actual impedance is consistently low, a target of 105–110 Ω should compensate for second order effects. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 178: Distance From Intel 82562Et To Magnetics Module
The signals can be routed through 75 Ω resistors to the plane. Stray energy on unused pins is then carried to the plane. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 179: Termination Plane Capacitance
1000 Vac. Figure 127. Termination Plane RJ-45 Magnetics m odule Term ination plane Additional capacitance that m ay be required for EFT testing LAN_term_plane ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 180: Intel ® 82562 Et/Em Disable Guidelines
100 Ω resistor. The remaining 3 control signals should each be connected thru 100 Ω series resistors to the common node “82562ET/EM_Disable” of the disable circuit. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 181: 82562Et / 82562Eh Dual Footprint Guidelines
TQFP ICH2 LAN_RXD[2:0] LAN_TXD[2:0] Stub LAN _dual-footprint_conn Figure 130. Dual Footprint Analog Interface 82562EH/82562ET 82562EH RJ11 Ring config. Magnetics m odule 82562ET RJ45 config. LAN_dual_footprint_analog_IF ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 182 • Traces from magnetics to connector must be shared and not stubbed. An RJ-11 connector that fits into the RJ-45 slot is available. Any amount of stubbing will destroy both HomePNA* and Ethernet performance. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 183: Intel ® Ich2 Routing Guidelines - Four-Layer Motherboard
I/O Controller Hub 2 ® 9.10 Intel ICH2 Routing Guidelines – Four-Layer Motherboard ® Figure 131. Example Intel ICH2 Top Layer Breakout Using Standard Size Vias Top Layer ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 184: Figure 132. Example Intel ® Ich2 Bottom Layer Breakout Using Standard Size Vias
I/O Controller Hub 2 ® Figure 132. Example Intel ICH2 Bottom layer Breakout Using Standard Size Vias Bottom Layer ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 185: Fwh Guidelines
3.3 V plane to which the rest of the power pins are connected. This circuit also allows the board to operate with 3.3 V on this pin during normal operation. Figure 133. FWH VPP Isolation Circuitry 3.3V ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 186: Intel ® Ich2 Decoupling Recommendations
Glue Chip 4 (Intel ICH2 Glue Chip) In order to reduce the component count and BOM cost of the Intel 850 chipset based-platform, Intel has developed an ASIC component that integrates miscellaneous platform logic into a single chip. The Glue Chip 4 is designed to integrate some or all of the following functions into a single device.
Page 187: Spkr Pin Consideration
SPKR pin until POWEROK is in a stable high state. This would allow a weak effective load to be implemented. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 188: 1.8 V And 3.3 V Power Sequence Requirement
If one of these signals goes high while one of its associated power planes is active and the other is inactive, a leakage path will exist between the active and inactive power wells. This could result in high, possibly damaging internal currents. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 189: Pirq Routing
Figure 136 is an example. It is up to the board designer to route these signals in a way that is the most efficient for their particular system. A PCI slot can be routed to share interrupts with any of the ICH2’s internal device/functions. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 190 I/O Controller Hub 2 This page is intentionally left blank. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 191: Additional Design Considerations
In addition they also document the keepouts. A 0.409 inch diameter routing keepout should be maintained on the secondary side of the board. The retention holes should be a non-plated hole. Figure 139 illustrates the hole locations and keepouts for the Intel 850 chipset heatsink retention mechanism. For heatsink volumetric ® ®...
Page 192: Figure 137. Rm Keepout Drawing 1
Additional Design Considerations Figure 137. RM Keepout Drawing 1 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 193: Figure 138. Rm Keepout Drawing 2
Additional Design Considerations Figure 138. RM Keepout Drawing 2 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 194: Figure 139. Intel ® Mch Keepouts And Rm Hole Locations
Additional Design Considerations ® Figure 139. Intel MCH Keepouts and RM Hole Locations ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 195: Power Header For Active Cooling Solutions
+12 V No Connect The Intel boxed processor heatsink includes an integrated fan. The recommended connector for the active cooling solution is a Walden*/Molex* 22-23-2037, AMP* 640456-3 or equivalent. The integrated fan requires the system board to supply a minimum of 740mA at 12V for proper operation.
Page 196 Additional Design Considerations This page is intentionally left blank ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 197: Intel ® Pentium
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines ® ® Intel Pentium 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.1 Power Requirements ® ® Intel recommends using an Intel Pentium 4 Processor VR Down Design Guidelines-compliant regulator for the processor system board designs that meets FMB2 requirements (refer to Section ®...
Page 198: Fmb1 Vr Component Placement
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.1.1 FMB1 VR Component Placement Figure 140. FMB1 VR Component Placement ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 199: Fmb2 Vr Component Placement
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.1.2 FMB2 VR Component Placement Figure 141. Four-Phase VR Component Placement Figure 142. Three-Phase VR Component Placement ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 200: Fmb1 Decoupling Requirements
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.1.3 FMB1 Decoupling Requirements For the processor voltage regulator circuitry to meet the transient specifications of the processor, proper bulk and high frequency decoupling is required. The decoupling requirements for the processor power delivery in this case are shown in Table 46.
Page 201: Figure 143. Decoupling Placement
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 143. Decoupling Placement ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 202: Fmb2 Decoupling Requirements
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.1.4 FMB2 Decoupling Requirements In order for the processor voltage regulator circuitry to meet the transient specifications of the processor, proper bulk and high frequency decoupling is required. The decoupling requirements for the processor power delivery in this case are described in Table 48 and Table 49.
Page 203: Figure 144. Four-Phase Decoupling Placement
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Table 51. Three-Phase Decoupling Locations Type Number Location 560µF OSCONs* North side of the processor as close as possible to the keep-out area for the retention mechanism AI Electrolytic, 3300 µF...
Page 204: Figure 145. Three-Phase Decoupling Placement
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 145. Three-Phase Decoupling Placement ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 205: Fmb1 Layout (6-Layer Board)
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.1.5 FMB1 Layout (6-Layer Board) All six layers in the processor area should be used for power delivery. Four layers should be used for VCC_CPU and two layers should be used for ground. Traces are not sufficient for supplying power to the processor due to the high current and low resistance required to meet the processor voltage specifications.
Page 206: Figure 147. Layer 2 Power Delivery Shape (Vss)
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 147. Layer 2 Power Delivery Shape (VSS) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 207: Figure 148. Layer 3 Power Delivery Shape (Vcc_Cpu And Vss)
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 148. Layer 3 Power Delivery Shape (VCC_CPU and VSS) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 208: Figure 149. Layer 4 Power Delivery Shape (Vcc_Cpu And Vss)
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 149. Layer 4 Power Delivery Shape (VCC_CPU and VSS) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 209: Figure 150. Layer 5 Power Delivery Shape (Vss)
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 150. Layer 5 Power Delivery Shape (VSS) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 210: Figure 151. Bottom Layer Power Delivery Shape (Vcc_Cpu)
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 151. Bottom Layer Power Delivery Shape (VCC_CPU) The high frequency decoupling capacitors should be placed with alternating VCC_CPU and VSS to provide a better path for power delivery through the capacitor field. An example of this placement is shown in Figure 152.
Page 211: Figure 152. Alternating Vcc_Cpu/Vss Capacitor Placement
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 152. Alternating VCC_CPU/VSS Capacitor Placement = Vcc = Vss ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 212: Fmb2 Four-Phase Layout (4-Layer Board)
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.1.6 FMB2 Four–Phase Layout (4-Layer Board) All four layers in the processor area should be used for power delivery. Two layers should be used for VCC_CPU and two layers should be used for ground. Traces are not sufficient for supplying power to the processor due to the high current and low resistance required to meet the processor voltage specifications.
Page 213: Figure 154. Layer 2 Power Delivery Shape (Vss)
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 154. Layer 2 Power Delivery Shape (VSS) Figure 155. Layer 3 Power Delivery Shape (VSS) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 214: Fmb2 - Three-Phase Layout (4-Layer Board)
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 156. Bottom Layer Power Delivery Shape (VCC_CPU) 11.1.7 FMB2 – Three-Phase Layout (4-Layer Board) All four layers in the processor area should be used for power delivery. Two layers should be used for VCC_CPU and two layers should be used for ground.
Page 215: Figure 157. Top Layer Power Delivery Shape (Vcc_Cpu)
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 157. Top Layer Power Delivery Shape (VCC_CPU) Figure 158. Layer 2 Power Delivery Shape (Vss) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 216: Figure 159. Layer 3 Power Delivery Shape (Vss)
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 159. Layer 3 Power Delivery Shape (Vss) Figure 160. Bottom Layer Power Delivery Shape (VCC_CPU) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 217: Fmb1 - Common Layout Issues
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.1.8 FMB1 – Common Layout Issues The processor socket has 478 pins with 50-mil pitch. The routing of the signals, power and ground pins will require creation of many vias. These vias cut up the power and ground planes beneath the processor resulting in increased inductance of these planes.
Page 218: Figure 162. Routing Of Vr Feedback Signal
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 162. Routing of VR Feedback Signal ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 219: Fmb2 - Common Layout Issues
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.1.9 FMB2 - Common Layout Issues The processor socket has 478 pins with 50-mil pitch. The routing of the signals, power and ground pins will require creation of many vias. These vias cut up the power and ground planes beneath the processor resulting in increased inductance of these planes.
Page 220: Thermal Considerations
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 164. Routing of VR Feedback Signal 11.2 Thermal Considerations 11.2.1 FMB1 For a power delivery solution to meet the flexible motherboard (FMB) requirements, it must be able to delivery a fairly high amount of current. This high amount of current also requires that the solution is able to dissipate the associated heat generated by the components and keep all of the components and the PCB within their thermal specifications.
Page 221: Fmb2 - Voltage Regulator Thermal Protection Circuit
The VR_TDC limits of the system board are typically governed by the system board thermal limits. Intel recommends that system boards designed to the above guidelines implement a VR thermal monitor circuit. Note: The specifications for the Pentium 4 processor with 512-KB L2 Cache on 0.13 micron process are ® ®...
Page 222: Figure 165. Example Circuit That Can Be Used As A Thermal Monitor
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 165. Example Circuit That Can Be Used As a Thermal Monitor Vccp 130Ω PROCHOT# 1kΩ 680Ω 1kΩ LM393 130Ω 3904 499Ω 7.5kΩ 6.8k 0.1uF THMSTR For this circuit implementation, the thermistor (THMSTR) should be placed in the hottest area of the VR.
Page 223: Simulation
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.3 Simulation 11.3.1 FMB1 To completely model the system board, one must include the inductance and resistance that exists in the cables, connectors, PCB planes, pins and body of components (such as resistors and capacitors), processor socket, and the voltage regulator module.
Page 224: Fmb2
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.3.2 FMB2 To completely model the system board, one must include the inductance and resistance that exists in the cables, connectors, PCB planes, pins and body of components (such as resistors and capacitors), processor socket, and the voltage regulator module.
Page 225: Filter Specifications For Vcca, Vcciopll, And Vssa
VCCIOPLL filter design. Note: The 1 µF package capacitor in Figure 168 does not exist on the Pentium 4 processor in the 478-pin package. It is present for the Pentium 4 processor with 512-KB L2 cache on .13 micron process only.
Page 226: Figure 169. Filter Recommendation
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 169. Filter Recommendation 0.2 dB 0 dB 0.5 dB Forbidden Zone Forbidden Zone -28 dB -34 dB 1 Hz fpeak 1 MHz 66 MHz fcore passband high frequency...
Page 227: Figure 170. Example Component Placement For Pll Filter
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines Figure 170. Example Component Placement for PLL Filter ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 228 Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines This page is intentionally left blank. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 229: Power Distribution Guidelines
12.2 Power Management The Intel 850 chipset-based platform implements the ACPI mechanisms software and hardware that enables the system to minimize system power consumption, manage system thermal limits, and maximize the battery life. This implementation involves tradeoffs among system speed and noise.
Page 230: Acpi Hardware Model
12.2.1 ACPI Hardware Model The Intel 850 chipset-based desktop supports both legacy and ACPI operations, which involves sequencing the platform between the various global system states (G0–G3). Figure 171 depicts global states and the transitions. For complete detail of the mechanisms involved in transition from any of the global states refer to the ACPI Interface Specification 1.0a, Section 4.5.
Page 231: 1.8 V Rac Isolation Solution
Power Distribution Guidelines ® ® Table 55. Intel 850 Chipset and Intel ICH2 Thermal Design Power Parameter Icc Max Sustainable Current (A) S0) • MCH (UP) Typical Thermal Design Power = 5.8 W • MCH (UP) Maximum Thermal Design Power = 8.0 W 1.8 V Core...
Page 232: Figure 173. Ferrite Bead Filter Circuit
0805 components except for the 10 µF capacitor, which is a 1206 size component. ® Table 56. Intel MCH 1.8 V RAC Pinout Channel A Channel B ® 1.8 V RAC Intel Pinout Location Ball ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 233: Figure 174. Customer Reference Board Layout Example
MCH package package Decoupling Decoupling Caps for Caps for 1.8V 1.8V Power Power Figure 175. Customer Reference Board Layout Example (Bottom – Layer 6) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 234: Vterm/Vdd Power Sequencing Requirement
Core. A Schottky diode can be placed between the 1.8 V and 2.5 V to ensure this power-up sequence. Figure 177. 1.8 V and 2.5 V Power Sequence (Schottky Diode) 1.8V 2.5V ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 235: Intel ® 850 Chipset Power Sequencing Requirements
VDDQ and VTT supplies. Figure 178. Desired Mode of Power Sequencing VCC1_8 Voltage VDDQ/VTT Time Figure 179. Optional Mode of Power Sequencing VCC1_8 Voltage VDDQ/VTT 1.0V 1.0V Time ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 236: Intel ® Ich2 V5Ref And Vcc3.3 Sequencing Requirement
V5REF_SUS can be connected to either VccSus3_3 or 5 V_Always/5V_AUX rails. Figure 180. V5REF Sequencing Circuit Vcc3.3 VCC5 To system To system VREF 5Vref_circ ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 237: Cpu / Ck00 Power Sequencing Requirement
CK00 clock chip powers up. An example circuit is shown below. Figure 181. CPU/CK00 Sequencing Circuit VCC3_CLK 47K 5% CLK_PWRDWN CK00 Clock Chip / DRCG MBT3904 DUAL VCCP 4.7K 5% ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 238 Power Distribution Guidelines This page is intentionally left blank. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 239: Debug Port Routing Guidelines
Debug Port Routing Guidelines Debug Port Routing Guidelines In Pentium 4 processor in the 478-pin package based systems, the debug port should be implemented as an on-board debug port. ® Refer to the latest revision of the Pentium 4 Processor in the 478-pin Package Debug Port Design Guide for details on the implementation of the debug port.
Page 240 Debug Port Routing Guidelines This page is intentionally left blank. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 241: Debug Tools Specifications
14.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging the Pentium 4 processor in the 478-pin package systems. Tektronix* and Agilent* should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature.
Page 242 Debug Tools Specifications This page is intentionally left blank. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 243: Schematic Review Checklist
• AGTL+ common clock I/O signal • Connect to MCH • AGTL+ common clock I/O signal BNR# • Connect to MCH • AGTL+ common clock input signal BPRI# ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 244 Schematic Review Checklist Checklist Items Recommendations Reason/Impact/Documentation • Terminate to VCC_CPU with a 51 Ω • The Intel 850 chipset contains on-die BR0# 5% resistor near the processor. termination for the BR0# signal. The Connect to the MCH. processor does not contain on-die termination for this particular AGTL+ signal;...
Page 245 • Connect to ICH2. • Asynch GTL+ input signal SLP# • No pull-up required. • Refer to Section 5.4.1.2. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 246 • This voltage powers the processor dynamic VID circuitry. ® ® • Connect to VR or VRM. These are • Refer to the Intel [4:0] Pentium open-drain signals from the processor Processor in the 478-Pin Package VR and require pull-ups to 3.3 V for Down Design Guidelines.
Page 247 For systems that incorporate a debug port, 51 Ω 5% termination is required near the ® debug port as well. Refer to the Intel ® Pentium 4 Processor in the 478-pin Package Debug Port Guidelines for further details.
Page 248: Ck00 Clock Generator Checklist
• Connect differential clock pair to processor, MCH, ITP connector. 3.3 V(VCC) • Connect to 3.3 V power plane • Connect to GND plane. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 249: Direct Rambus Clock Generator (Drcg1 And Drcg2) Checklist
• Connect to 1.8 V power plane. • This is a voltage reference for PclkM and SynclkN signals. • Terminate to 1.8 V power plane with • This function is not used for Intel 850 STOPB# a 4.7 k Ω resistor. chipset-based platform.
Page 250 Mult[1:0] PLL divider ratio in the DRCG. Connection to GPIO allows software adjustable PLLCLK and REFCLK multipliers. • The Intel 82850 chipset platform supports 400 MHz (PC800) and 300 MHz (PC600) RAMBUS operation only. • The Intel 82850E chipset platform...
Page 251: Intel ® 850 Chipset Checklist
V • Decouple the voltage divider with a 1 µf capacitor. • Keep the voltage divider within 1.5 inches of the MCH V ball. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 252 MCH package (within 150 mils) 1.8 V RAC Power • Option 1 — Low pass filter with • The Intel 850/850E chipset requires a low-pass filter on the V Isolation inductor: Place 3.3 nH inductor pins to meet clock jitter between V RAC and the 1.8 V power...
Page 253: Agp Checklist
G_REF[1:0] • Refer to Section 7.1.7. pins on the MCH. • Intel 850 chipset only supports 1.5 V • Refer to Section 7.1.6. TYPEDET# [A2] add-in card. Therefore, TYPEDET# detection on the motherboard is not required.
Page 254 • In the MCH, weak pull-ups are SBA[7:0] AGP connector. integrated for SBA[7:0] signals. These signals implement internal pull-ups of a nominal value of 8 k Ω . ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 255: Rambus Rimm* Connector Checklist
• Refer to the RAMBUS datasheets at either: http://www.rambus.com  Provide proper isolation on SCL /SDA and pull SVDD to 3.3 V  Tie SVDD to 3.3V ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 256 • V can be generated with a CMOS voltage divider consisting of a 36 Ω pull-up resistor to VCC2_5 and 100 Ω resistor to GND. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 257 0.1 µF capacitors per 2 RSL signals.  2 x 10 µF MLC • PC1066 Low frequency decoupling:  2 x 100 µ F tantalum capacitors ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 258 • MCH: Locally – A value of 0.1 µ F is required for local decoupling and a 100 Ω series resistor is required near the MCH, but before the voltage divider circuit. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 259: Intel ® Ich2 Checklist
• Allows BIOS to set the 4:3 Host-to- GPOx to RDRAM Device Clock Generator RDRAM devicefrequency ratio for pins Mult0, Mult1 133 MHz system bus operation ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 260: Hub Interface
EE_DOUT of EEPROM or CNR resistor for this signal. Connector. • Connected to EEPROM data output signal • (Output from EEPROM perspective and input from ICH2 perspective) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 261: Fwh/Lpc Interface
Recommend a 2.7 k Ω pull- PIRQ#[E] controllers, they cannot be used as up resistor to VCC5 or 8.2 k Ω to GPIO(s) pin. VCC3_3. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 262: Gpio
Schematic Review Checklist Checklist Items Recommendations Reason/Impact Pentium 4 processor based systems: If the APIC is not used on UP APIC systems: • These processors do not have APIC pins so all platforms using this • Use pull downs for each APIC signal.
Page 263: Usb
• Connect to the processor’s • Refer to processor documentation CPUPWRGD CPUPWRGD input. Requires weak of the processor that platform external pull-up resistor. utilizes for specific values. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 264: System Management
• Route to Test Point if SUSCLK is • To assist in RTC circuit debug SUSCLK unused ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 265: Intel
• Route to a test point. • ICH2 contains an integrated pull-up FS[0] for this signal. Test point used for manufacturing appears in XOR tree. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 266: Power
VREF[2:1]. V5REF must power up be used to ensure the proper before or simultaneous to VCC3_3. It V5REF sequencing. must power down after or simultaneous to VCC3_3. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 267: Ide Interface
• Device Side Detection will have the capability to detect  Connect a 0.047 µ F capacitor from cables IDE pin PDIAG/CBLID to GND. No ICH2 connection. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 268 Schematic Review Checklist This page is intentionally left blank. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 269: Layout Review Checklist
Layout Review Checklist This checklist highlights design considerations that should be reviewed prior to manufacturing a motherboard that implements an Intel 850 chipset. The items contained within this checklist attempt to address important connections to these devices and any critical supporting circuitry.
Page 270 BINIT# BNR# BPM[5:0]# BR0# DBSY# DP[3:0]# DRDY# HIT# HITM# LOCK# MCERR# • All signals impedance’s should equal • Refer to Chapter 2. 50 Ω ±15% ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 271: Asynchronous Gtl+ And Other Signals
• Place 51.1 Ω ±1% resistors as close to • Refer to Section 5.4.1 COMP[1:0] as possible 16.1.3 Processor Keep-Out Zones √ Recommendations Reason/Impact/Documentation • Refer to Chapter 10. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 272: Processor Decoupling
(within 150 mils) to the chipset These recommendations are only used for package. designs containing microstrip configurations. • Refer to Section 5.5.1 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 273: Agtl+ ( Vref Hdvref [3:0], Havref [1:0] And Ccvref)
• Keep other signals 10 mils away from V • V signal must be a clean as possible signal. from noise. • Refer to Section 5.3. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 274: Ck00 Routing Guidelines
• All host clocks must be ground referenced. • This ensures that proper current return path is available. • Refer to Section 4.1 ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 275 Z (5 –9 inches). Route signals on a single layer. • Refer to Section 4.4 and Section 4.4.2. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 276: Rambus Technology Routing Guidelines
• A RSL signal CAN NOT serpentine so tightly 10-mil ground isolation MUST be between that the signal is adjacent to itself with no serpentine segments ground isolation between the serpentines. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 277 • RSL traces do not cross power plane splits. • To maintain signal integrity. RSL signals must also not be routed next to a power plane split ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 278: Ground Isolation
• Ground isolation vias connect on all layers and should NOT have thermal relieves. • Ground pins in RIMM connector should connect on all layers. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 279: Layout
• 100 µF Tantalum capacitors must have at least 2 vias/capacitor to ground. • V • Refer to Section 6.1.3 island should be at least 50 mils wide TERM ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 280: Rambus Drcg* Clock Routing Recommendation
• CTM pair trace length: • Refer to Section 4.3.3.1.  DRCG-to-2 RIMM connector 0–6 inches  RIMM connector-to-RIMM* connector 0.4–1.0 inches  1st RIMM connector-to-MCH 1 inch–6 inches ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 281: Rambus Drcg* Layout (Clean Power Supply)
3.3 V DRC* power flood on the top layer • Ferrite bead isolating DRCG power flood • Refer to Section 4.3.4. from 3.3 V main power. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 282: Rambus Drcg* (Ctm/Ctm# Output Network Layout)
• 5mil trace width, 5 mil trace separation • Refer to Section 7.1.1. • No trace matching requirements for 1X • Refer to Section 7.1.1. signals. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 283: 2X/4X Signals
• Refer to Section 7.1.9. signals. • Pour a Ground flood under the V plane • Optimizes the mutual inductance between two planes. • Refer to Section 7.1.4. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 284: Agp Interface Greater Than 6 Inches And Less Than 7.25 Inches
• Pour a VSS flood under V plane to • To help lower inductive path from the decouple AGP. decoupling capacitor. • Refer to Section 7.1.4. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 285: Agp Connector Decoupling
• Refer to Section 8.2.5. (MCH and ICH2) spread over the Hub Interface. • Place within 150 mils of each package. • Refer to Section 8.2.5. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 286: Ide Interface
• 5 mil trace width, 5 mil spacing between • Refer to Section 9.3. traces • Max Trace Length • Refer to Section 9.3. ICH2/Codec/CNR = 12 inches ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 287: Usb
• Refer to Section 9.12. included in Hub decoupling • Place Decoupling capacitors as close to the • Refer to Section 9.12. ICH2 as possible (~ 400 mils) ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 288: Rtc
If a 90 degree bend is required, it is recommended to use two 45 degree bends. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 289: Miscellaneous
• 5 V Reference: two 0.1 µF capacitors • Refer to Section 9.12. • 5 V Reference Stand By: one 0.1 µF • Refer to Section 9.12. capacitor ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 290 Layout Review Checklist This page is intentionally left blank. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 291: Appendix A: Reference Schematics
Appendix A: Reference Schematics Appendix A: Reference Schematics The following pages contain reference schematics for both 4 layer and 6 layer 82850 platforms. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 292 Appendix A: Reference Schematics This page is intentionally left blank. ® ® ® Intel Pentium 4 Processor / Intel 850 Chipset Family Platform Design Guide...
Page 365 INTEL(R) 850 MPGA478 CUSTOMER REFERENCE BOARD...

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