Sdc - Intel 460GX Software Developer’s Manual

Register Descriptions
2.5.2

SDC

2.5.2.1 FSB_D_PMC_[1,0]: System Bus Performance Monitor Configuration
Register
Bus CBN, Device Number: 04h
Address Offset:
Default Value:
The FSB_D_PMC_[1,0] Registers specify the configuration of the SDC system bus performance
monitors. This includes specifying Event Selection, Unit Mask, Enable & Divisible Source &
Reload Control.
Bits
23:17
16:15
14:8
7
6:5
2-34
98-9Ah, 9C-9Eh
000000h each
Description
reserved(0).
Mask.
This field contains the Event Specific Mask Bits. This allows qualifying event collection
by the issuing agent of the transaction.
00b reserved.
01b Monitor only if 460GX chipset initiated the transaction.
10b Monitor only if 460GX chipset did not initiate the transaction.
11b Monitor all transactions regardless of issuing agent.
Event Select.
Selects the event to be monitored.
000 0000b Monitoring Disabled.
000 0001b System Bus Clocks.
000 0010b DBSY# Clocks.
100 0010b DBSY# Events.
000 0011b DRDY# Clocks.
100 0011b DRDY# Events.
100 0100b DBSY# and not(DRDY#) Events.
000 0101b TRDY# Clocks.
100 0101b TRDY# Events.
000 0110b TRDY# asserted when DBUSY# asserted (clocks)
100 0110b TRDY# asserted when DBUSY# asserted (events)
000 0111b Read from SDC waiting on processor write (clocks)
100 0111b Read from SDC waiting on processor write (events)
000 1000b Read from SDC waiting on an SDC read to complete (clocks)
100 1000b Read from SDC waiting on an SDC read to complete (events)
100 1001b reserved
100 1010b reserved
000 1011bEvent Logic 0 Active Clocks
100 1011b Event Logic 0 Events
000 1100b Event Logic 1 Active Clocks
100 1100b Event Logic 1 Events
reserved(0).
Disable Source.
Selects event that will disable the performance monitor. Note that the disable and enable
sources are edge-triggered for Event 0 or 1.
00b Never Disable.
Size:
Attribute:
Intel® 460GX Chipset Software Developer's Manual
24 bits each
Read/Write