Page 1 Intel® 460GX Chipset System Software Developer’s Manual June 2001 Document Number: 248704-001...
Page 2 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Page 3: Table Of Contents
Performance Monitor Registers...2-30 2.5.1 SAC ...2-30 2.5.2 SDC...2-34 2.5.3 PXB ...2-36 2.5.4 GXB...2-38 2.5.5 WXB ...2-43 Interrupt Related Registers ...2-44 2.6.1 SAC ...2-44 2.6.2 PID PCI Memory-mapped Registers ...2-45 2.6.3 PID Indirect Access Registers...2-46 Intel® 460GX Chipset System Software Developer’s Manual...
Page 4 Hardware Initialization ...5-7 5.5.4 Memory Scrubbing ...5-7 Data Integrity and Error Handling...6-1 Integrity ...6-1 6.1.1 System Bus ...6-1 6.1.2 DRAM...6-2 6.1.3 Expander Buses ...6-2 6.1.4 PCI Buses ...6-2 6.1.5 AGP...6-2 Slot Power-down and Disable ...3-7 Intel® 460GX Chipset System Software Developer’s Manual...
Page 5 6.12.7 Error Determination and Logging ...6-29 6.12.8 Error Conditions ...6-30 AGP Subsystem ...7-1 Graphics Address Relocation Table (GART) ...7-1 7.1.1 GART Implementation...7-3 7.1.2 Programming GART...7-4 7.1.3 GART Implementation...7-5 7.1.4 Coherency ...7-5 7.1.5 Interrupt Handling...7-6 Intel® 460GX Chipset System Software Developer’s Manual...
Page 6 Serial Input Byte Data ...8-16 8.2.8 Serial Input Byte Pointer ...8-17 8.2.9 General Purpose Output ...8-17 8.2.10 Hot-Plug Non-interrupt Inputs ...8-17 8.2.11 Hot-Plug Slot Identifier ...8-17 8.2.12 Hot-Plug Switch Interrupt Redirect Enable...8-18 8.2.13 Slot Power Control ...8-18 Intel® 460GX Chipset System Software Developer’s Manual...
Page 7 11.1.11 BIOSEN–BIOS Enable Register (Function 0) ...11-5 11.1.12 PIRQRC[A:D]–PIRQx Route Control Registers (Function 0) ...11-5 11.1.13 SerIRQC–Serial IRQ Control Register (Function 0) ...11-6 11.1.14 TOM–Top of Memory Register (Function 0)...11-6 11.1.15 MSTAT–Miscellaneous Status Register (Function 0)...11-7 Intel® 460GX Chipset System Software Developer’s Manual...
Page 8 PCI Configuration Registers (Function 2) ...13-1 13.2 USB Host Controller Register Descriptions (PCI Function 2) ...13-2 13.2.1 VID–Vendor Identification Register (Function 2) ...13-2 13.2.2 DID–Device Identification Register (Function 2) ...13-2 13.2.3 PCICMD–PCI Command Register (Function 2) ...13-2 viii Intel® 460GX Chipset System Software Developer’s Manual...
Page 9 14.3.6 smbhstdat0–SMBus Host Data 0 Register (I/O)...14-9 14.3.7 smbhstdat1–SMBus Host Data 1 Register (I/O)...14-10 14.3.8 smbblkdat–SMBus Block Data Register (I/O) ...14-10 14.3.9 smbslvcnt–SMBus Slave Control Register (I/O)...14-10 14.3.10 smbslvdat–SMBus Slave Data Register (I/O) ...14-11 Intel® 460GX Chipset System Software Developer’s Manual...
Page 10 16.2.6 Entry/Exit for the S4 and S5 States...16-4 16.3 Handling of Power Failures in IFB...16-5 Figures Diagram of a Typical Intel® 460GX Chipset-based System with AGP ...1-1 System Memory Address Space...4-2 Itanium™ Processor and Chipset-specific Memory Space ...4-5 System I/O Address Space ...4-6 System Memory Address Space as Viewed from an Expander Bridge (PXB/GXB)...4-7...
Page 11 Drive PIO Capability as a Function of Cycle Time ...10-8 10-7 IFB Drive Mode Based on DMA/PIO Capabilities ...10-9 10-8 IDE Mode/Drive Feature Settings for Optimal DMA/PIO Operation ...10-10 10-9 DMA/PIO Timing Values Based on PIIX Cable Mode/System Speed...10-11 Intel® 460GX Chipset System Software Developer’s Manual...
Page 12 15-1 SERIRQ Frames ...15-9 15-2 RTC (Standard) RAM Bank...15-14 16-1 IFB Power States and Consumption ...16-1 16-2 Causes of SMI#...16-2 16-3 Causes of SCI# ...16-3 16-4 ACPI Bits Not Implemented in IFB ...16-4 Intel® 460GX Chipset System Software Developer’s Manual...
Page 13: Introduction
This document describes the software programmer's interface to the 460GX chipset. It provides a brief summary of the system architecture supported by the 460GX chipset, a list of features within the chipset and a detailed description of software or other externally visible segments.
Page 14: Component Overview
Introduction 1.1.1 Component Overview Table 1-1 lists the 460GX chipset components. Table 1-1. Intel® 460GX Chipset Components Component 82461GX System Address Controller 82462GX System Data path Controller 82463GX Memory Address Controller 82464GX Memory Data path Controller 82465GX Graphics Expander Bridge...
Page 15: Product Features
• Parity protection on address and control signals, ECC protection on the data signals. • GTL+ bus driver technology. Intel® 460GX Chipset Software Developer’s Manual Introduction • High bandwidth system bus for multiprocessor scalability — Support of the Intel® Itanium™ processor 64-bit data bus —...
Page 16: Dram Interface Support
Can be configured to provide two independent 32 bit, 33 MHz PCI buses or one 64 bit, 33 MHz PCI bus. • PCI Rev. 2.2, 5V tolerant (PXB drives 3.3 volts, but is 5.0 volt tolerant). Intel® 460GX Chipset Software Developer’s Manual...
Page 17: Wxb Features
ECC bits in DRAM accessible by diagnostics. • Fault recording of multiple errors; sticky through reset, but NOT through power-down. • Memory scrubbing implemented in hardware. • Boundary test capability through JTAG. • JTAG TAP port for debug. Intel® 460GX Chipset Software Developer’s Manual Introduction...
Page 18: Other Platform Components
I/O & Firmware Bridge (IFB) The 460GX chipset is designed to work with the IFB south bridge. As part of this support, the PXB includes an internal PCI arbiter as well as support for an external PCI arbiter. The IFB consists of an 8259C Interrupt controller, a bus-mastering IDE interface, and a Universal Serial Bus interface.
Page 19: Revision History
(http://www.usb.org) • System Management Bus Specification, Rev. 1.0 • Low Pin Count (LPC) Interface Specification, Rev 1.0 Note: Contact your Intel representative for the latest revision of the documents without document numbers. Revision History Date June 2001 Intel® 460GX Chipset Software Developer’s Manual Description Initial release.
Page 20 Introduction Intel® 460GX Chipset Software Developer’s Manual...
Page 21: Register Descriptions
I/O space; I/O accesses to these registers are translated by the 460GX chipset into appropriate PCI configuration cycles. To access a configuration register in the 460GX chipset (or any other I/O device), software first writes a value to the CONFIG_ADDRESS location consisting of the bus number, Device Number, function number and register number.
Page 22: Access Restrictions
Device Number within the bus, and the Register Number within the Device. Accesses to devices on Bus #0 and Bus #(CBN) are serviced by the 460GX chipset depending on their device number. Device 10h on Bus #0 is mapped to the SAC; it contains the programmable Chipset Bus Number.
Page 23: Register Attributes
2.2.4 Reserved or Undefined Register Locations In addition to reserved bits within a register, the 460GX chipset contains address locations in the PCI configuration space that are marked “Reserved” or are simply undefined. Several of the 460GX chipset devices are multi-function devices; all registers in the unused functions are considered “Reserved”.
Page 24: Consistency
When the address decode ranges of 460GX chipset devices are being updated, no other bus traffic is allowed over the address ranges being affected by the update. This means that the code that updates initial configuration must be executing from a location that will not be affected by the update.
Page 25: Config_Data: Configuration Data Register
Bus #0 is always reserved for programming the CBN. On the bus that the chipset is mapped into (determined by the CBN register), Device Numbers 0-31 are reserved for the 460GX chipset components as shown in forwarded to the selected bus.
Page 26 SAC-to-SDC data bus. Function: Size: Attribute: Locked: Function: Size: Attribute: Locked: Intel® 460GX Chipset Software Developer’s Manual Section 6 for the usage 8 bits Read Only/Write Clear, Read/Write Section 6 for the usage 8 bits...
Page 27 SDC Fatal Error (SFE) Fatal error in SDC. ‘Completion’ Command Underflow; MAC A, Stack L (CCAL) ‘Completion’ Command Underflow; MAC A, Stack R (CCAR) ‘Completion’ Command Underflow; MAC B, Stack L (CCBL) Intel® 460GX Chipset Software Developer’s Manual Function: Size: 000000h Attribute:...
Page 28 Bus CBN, Device Number: 00h Address Offset: Default Value: Sticky: This register records all error conditions detected in the SAC/SDC. Bits Description 31:0 See FERR_SAC for bit definitions. Function: Size: 000000h Attribute: Locked: Intel® 460GX Chipset Software Developer’s Manual 32 bits Read/Write Clear...
Page 29 CAM and RAM associated with the ITID that is written into this register. Bits Description reserved (0) ITID This is the ITID that is used to address the CAM/RAM structure. Intel® 460GX Chipset Software Developer’s Manual Function: Size: undefined after Attribute: Locked:...
Page 30 Note: Note: if the P2P bit is not set, then bits [34:12] and [76] are not defined, since the transaction originated on the system bus and not the Expander bus. 2-10 Function: Size: undefined Attribute: Locked: Intel® 460GX Chipset Software Developer’s Manual 128 bits Read Only...
Page 31: Sdc
0 in the SDC. Bits Description 15:9 reserved(0) DC - Data Chunk of ITID. ITID - ITID of error. Intel® 460GX Chipset Software Developer’s Manual 40-47h Size: 64 bits Attribute: Read Only, New Value Latched anytime appropriate FERR register...
Page 32 59-5Ah Size: 16 bits Attribute: Read Only, New Value Latched anytime appropriate FERR register bit is set 60-67h Size: 64 bits Attribute: Read Only, New Value Latched anytime appropriate FERR register bit is set Intel® 460GX Chipset Software Developer’s Manual...
Page 33 This register records and latches the data corresponding to the first DED detected by memory interface 1 in the SDC. Bits Description 63:0 DE - System Data of Error. Intel® 460GX Chipset Software Developer’s Manual Size: 8 bits Attribute: Read Only, New Value Latched anytime appropriate FERR register...
Page 34 Read Only, New Value Latched anytime appropriate FERR register bit is set 79-7Ah Size: 16 bits Attribute: Read Only, New Value Latched anytime appropriate FERR register bit is set 80-83h Size: 0000h Attribute: Intel® 460GX Chipset Software Developer’s Manual 32 bits Read/Write to Clear...
Page 35 All four data port map to this bit. PDB - Data Parity Error (DPE) Parity Error Detected on transfer of Data from SAC to SDC. Intel® 460GX Chipset Software Developer’s Manual Register Descriptions 2-15...
Page 36 FERR register bit is set half of the double–pumped transfer. Size: 8 bits Attribute: Read Only, New Value Latched anytime appropriate FERR register bit is set Intel® 460GX Chipset Software Developer’s Manual 32 bits Read/Write to Clear half of the double-pumped...
Page 37 0. To test, this register is written with a masking function. All subsequent writes into memory will store a masked version of the computed ECC. Subsequent reads of memory locations written Intel® 460GX Chipset Software Developer’s Manual half of the double-pumped transfer. Otherwise, half of the double-pumped transfer.
Page 38 ECC checking at power-on. Bits Description Private Bus parity detection enable. Front Side Bus ECC correction/detection enable. 2-18 Size: 8 bits Attribute: Read/Write Size: 8 bits Attribute: Read/Write Size: 8 bits Attribute: Read/Write Intel® 460GX Chipset Software Developer’s Manual...
Page 39 SDC. Bits Description 15:9 reserved(0) DC - Data Chunk of ITID. ITID - ITID of error. Intel® 460GX Chipset Software Developer’s Manual D0-D7h Size: 64 bits Attribute: Read Only, New Value Latched anytime appropriate FERR register...
Page 40 E9-EAh Size: 16 bits Attribute: Read Only, New Value Latched anytime appropriate FERR register bit is set F0-F7h Size: 64 bits Attribute: Read Only, New Value Latched anytime appropriate FERR register bit is set Intel® 460GX Chipset Software Developer’s Manual...
Page 41: Mac
This register records the first error condition detected in the MAC. Bits Description reserved(0) Que-Overflow Error Signals that the MAC received too many commands from the SAC. Intel® 460GX Chipset Software Developer’s Manual Size: 8 bits Attribute: Read Only, New Value Latched anytime appropriate FERR register...
Page 42: Pxb
SERR# in the ERRCMD register. This bit remains set until explicitly cleared by software writing a 1 to this bit. 2-22 Function Number: 00h,01h Size: 0000h Attribute: Size: 8 bits Attribute: Read/Write Clear, Sticky Intel® 460GX Chipset Software Developer’s Manual 24 bits Read...
Page 43 PXB will return a normal response (with data of all 1’s for a read). In either case, an error flag is set in the PCISTS register. Default=0. Intel® 460GX Chipset Software Developer’s Manual cycles, per the PCI spec). If the data (Section 2.5.3.3,...
Page 44: Gxb
FERR_AGP: First Error Status Register for AGP Function Number: Address Offset: 2-24 BFN+1 Size: Attribute: Locked: BFN+1 Size: 00h each Attribute: Locked: clock timeout. BFN+1 Size: Intel® 460GX Chipset Software Developer’s Manual 8 bits Read/Write Clear 8 bits Read/Write Clear 8 bits...
Page 45 This register records all error conditions detected in the AGP interface after the first error. Errors recorded in FERR_AGP are not recorded here. Bits Description See FERR_AGP for definition of these bits. Intel® 460GX Chipset Software Developer’s Manual Attribute: Locked: BFN+1 Size:...
Page 46 PCI Data - Data of Error. 2-26 BFN+1 Size: 00h each Attribute: Locked: BFN+1 Size: 0000000000h each Attribute: Locked: BFN+1 Size: 00h each Attribute: Locked: Intel® 460GX Chipset Software Developer’s Manual 8 bits Read/Write Clear 64 bits Read/Write 64 bits Read/Write...
Page 47: Wxb
This flag is set when the Performance Monitor #0 detects an event. The PCI_WXB_PMC0 registers describes the conditions that can cause this to occur. This bit remains set until explicitly cleared by software writing a 1 to this bit. Default = 0. Intel® 460GX Chipset Software Developer’s Manual Size: Attribute:...
Page 48 1 to the specific bit location it wishes cleared. The response to 2-28 45h– 46h Size: 8040h Attribute: Size: Attribute: Intel® 460GX Chipset Software Developer’s Manual 16 bits Read/Write 8 bits Read/Write Clear, Sticky...
Page 49 Description See the FEPCI register description for definitions. Error logging is not performed for Next Error occurrences. Intel® 460GX Chipset Software Developer’s Manual Section 6.12 for information on the conditional reporting of these clock timeout timer expires. This flag may be configured to...
Page 50: Data Register
A5h–ADh Size: 000000000000000000h Attribute: AFh – B3h Size: 0000000000h Attribute: Function: 90-97h, 98-9Fh, Size: A0-A7h, A8-AFh, B0-B7h, B8-BFh 0 each Attribute: Locked: Intel® 460GX Chipset Software Developer’s Manual 72 bits Read/Write Clear, 40 bits Read/Write Clear, 64 bits each Read/Write...
Page 51 0 0001 1010 - Configuration Space - Monitor transactions Destined for Config Block 0 0000 1100 - Memory - Monitor transactions Destined for Memory 0 0001 1110 - Broadcasts - Monitor Broadcasts 1 0000 0000 - All Destinations - Monitor all Destinations Intel® 460GX Chipset Software Developer’s Manual (Section 2.5.1.2). D0-D7h, D8-DFh,...
Page 52 1R0 1100b SSBR 1R1 1101b RSBR 000 0001b Snoop events 000 0010b Snoop Stall events caused by 460GX chipset 000 0011b Snoop Stall events caused by processors 000 0100b Snoop Stall events by either CPU’s or GX 000 0101b Hit events from CPU...
Page 53 (110_0110b) and subtract out the number of reads that were to be retried but got a HITM# (code of 001_0111b). This give the exact number of reads that were retried on the bus. Intel® 460GX Chipset Software Developer’s Manual Register Descriptions 2-33...
Page 54: Sdc
This field contains the Event Specific Mask Bits. This allows qualifying event collection by the issuing agent of the transaction. reserved. Monitor only if 460GX chipset initiated the transaction. Monitor only if 460GX chipset did not initiate the transaction. Monitor all transactions regardless of issuing agent. 14:8 Event Select.
Page 55 This register contains the Performance Monitor Data Register. You may preset the value of the performance counter by writing to this register. You may read back the value of the performance counter by reading this register. Intel® 460GX Chipset Software Developer’s Manual A0-A7h, A8-AFh Size:...
Page 56: Pxb
Trigger. Start counting on the first rising edge of the selected event, and continue counting each clock cycle. 2-36 D8-DBh, E0-E3h Size: 0000_0000h each Attribute: DDh, E5h Size: 0000h each Attribute: Intel® 460GX Chipset Software Developer’s Manual 32 bits each Read/Write 8 bits each Read/Write...
Page 57 That is, unless otherwise noted for the specific event selected (below), the source or destination of the data must match the selection specified here for the transaction to be tracked. reserved Intel® 460GX Chipset Software Developer’s Manual E8 - EBh Size: 0000h each...
Page 58: Gxb
011 101 reserved RETRY 011 110 LOCK 011 111 ACK64 reserved BFN+1 50h, 58h Size: Attribute: Locked: Intel® 460GX Chipset Software Developer’s Manual reserved reserved reserved reserved Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write & Invalidate transactions...
Page 59 This bit is fed as an input into Event 1 logic. This bit is OR’ed with any other logic generating Event 1, guaranteeing that if this bit is set, then Event 1 will be asserted. Intel® 460GX Chipset Software Developer’s Manual BFN+1...
Page 60 10 0111b Count AGP clocks that both the low and high priority buffers are empty. 11 0000b Count AGP clocks that there are <=> ’n’ requests queued; using bits 31:24 and 19:18. 2-40 BFN+1 ECh, F0h Size: 000000h Attribute: Locked: Intel® 460GX Chipset Software Developer’s Manual 32 bits Read/Write...
Page 61 00b reserved. 01b Outbound. 10b Inbound. 11b Selects Both. 15:14 reserved(0). 13:8 Event Select Selects the event to be monitored. 00 0000b Monitoring Disabled Intel® 460GX Chipset Software Developer’s Manual BFN+1 Size: 000000h Attribute: Locked: Register Descriptions 24 bits Read/Write 2-41...
Page 62 001b Reload when counter overflows. 010b Reload on GXB Event 0 Asserted. 011b Reload on GXB Event 1 Asserted. 100b Reload on GXB Event 0 Asserting edge. 101b Reload on GXB Event 1 Asserting edge. 2-42 Intel® 460GX Chipset Software Developer’s Manual...
Page 63: Wxb
11 1111bAny Transaction 10:4 reserved (0) Enable Source When this bit is set to 1, the performance monitoring logic is enabled. Default=0. reserved (0) Intel® 460GX Chipset Software Developer’s Manual DCh – DFh Size: 00000000h Attribute: Not issued by WXB...
Page 64: Interrupt Related Registers
These bits represent the external task priority for symmetric agent ID 03h. 23:16 XTPR 2 These bits represent the external task priority for symmetric agent ID 02h. 2-44 E8h – EBh Size: 00000000h Attribute: Function: C0-C7h Size: Attribute: Locked: Intel® 460GX Chipset Software Developer’s Manual 32bits Read/Write 64 bits Read Only...
Page 65: Pid Pci Memory-Mapped Registers
Register Offset: FEC00000hDefault Value: [00000000h]Attribute: Read/Write Bit(s) Name 31:8 Reserved REGISTER ADDRESS Intel® 460GX Chipset Software Developer’s Manual Name Section 2.6.3. Software programs bits 7 through 0 of this register to select the Table 2-3. These 24 bits are reserved.
Page 66: Pid Indirect Access Registers
Registers at offsets 03h-0Fh are reserved and will return a 00h value when read. Table 2-6 summarizes the indirect access registers. Detailed descriptions of each register follow. 2-46 Description This 32-bit register contains the 32-bit write or read data value. Description Reserved Interrupt vector Intel® 460GX Chipset Software Developer’s Manual Table 2-4...
Page 67: Memory-Mapped Register Summary
RTE 22 RTE 23 RTE 24 RTE 25 RTE 26 RTE 27 RTE 28 RTE 29 RTE 30 RTE 31 RTE 32 Intel® 460GX Chipset Software Developer’s Manual Name Access Register Descriptions Default Value 00000000h 003F00vvh 00000000h 00000000h 00000000_00010000h 00000000_00010000h...
Page 68 (x)APIC ID value before using the PID in APIC mode. The (x)APIC ARBID register is also written during a write to this register. 2-48 Name Access Intel® 460GX Chipset Software Developer’s Manual Default Value 00000000_00010000h 00000000_00010000h 00000000_00010000h...
Page 69: I/O Apic Id Register Format
The PID APIC ARBID is always loaded with the PID APIC ID during a “INIT-level deassert” message. Note: Only four bits are required for the APIC ARBID. Bits 27:24 are used for this ID. Intel® 460GX Chipset Software Developer’s Manual Default Value: [00000000h]Attribute: Read/Write Description These four bits are reserved.
Page 70: I/O (X)Apic Arbitration Id Register Format
A 1 indicates that the buffer does not need to be flushed before the interrupt is sent out to the local (x)APIC. This setting will cause the hardware flush control signals to be ignored. Intel® 460GX Chipset Software Developer’s Manual...
Page 71 DELIVERY DELIVERY STATUS STATUS Intel® 460GX Chipset Software Developer’s Manual Description This bit masks the (x)APIC delivery of this interrupt. A 0 indicates that delivery of this interrupt is not masked. An edge or level on an interrupt pin that is not masked results in the delivery of the interrupt to the destination.
Page 72 A delivery mode of ExtINT requires an edge-triggered mode. ExtINT should be targeted for only one processor. This is the vector number identifying the interrupt being sent. Intel® 460GX Chipset Software Developer’s Manual...
Page 73: System Architecture
3.1.1 Processor Coherency Intel processors do not have a specific bit to specify coherency for each transaction. Data and code are usually considered fully coherent with respect to other processors and to each other. There are exceptions to this - such as the WC (write combining) memory type. Data that is marked as WC in the page table will not be coherent between processors.
Page 74: Pci Coherency
Non-coherent transactions are not required to be placed on the system bus (although they could be, with some loss of bus bandwidth). The 460GX chipset implementation does not pass non-coherent AGP traffic to the system bus. These addresses are sent directly to the memory queue. The processor could still have these addresses cached.
Page 75: Processor To Pci Traffic And Pci To Pci (Peer-To-Peer) Traffic
New EM code may be weakly ordered. To allow the processor to take advantage of this, the 460GX chipset defers all reads and returns the data out-of-order to the processor. By returning data in an out-of-order fashion, the DRAM’s may be accessed in an optimal manner. Accesses are sent out of the memory queue to free banks of SDRAM’s.
Page 76: Big-Endian Support
AGP to memory or transactions that stay within the non-locked PCI buses. The 460GX chipset does not support locks that cross device boundaries. In other words, if the first read in a locked sequence targets device X, then the remaining transactions in the lock (either R-W- W or W) must also target device X.
Page 77: Inbound Pci Locks
“posted” write until that data actually leaves the part. 3.6.2 Inbound PCI Locks The 460GX chipset does not support inbound locks. 3.6.3 Atomic Writes Some system bus operations such as Write 8 bytes, Write 16 bytes and Write 32 bytes, are indivisible operations on the system bus.
Page 78: Interrupt Delivery
The 4 XTPR registers in the 460GX chipset are updated when the processor does a special cycle on the bus. When the special cycle is decoded, the low order 3 bits of the DID are used to determine which register to update.
Page 79: Slot Power-Up And Enable
10. Gain ownership of the PCI bus through arbitration. 11. Clock the parallel latch. 12. Release ownership of the bus after 480 nsec. 13. Set PWREN inactive to the slot and clock the parallel latch. Intel® 460GX Chipset Software Developer’s Manual System Architecture...
Page 80 System Architecture Intel® 460GX Chipset Software Developer’s Manual...
Page 81: System Address Map
System Address Map Memory Map The Itanium™ processor supports a 44 bit address space. The 460GX chipset supports only 36 bits of the address bus for a 64 GB of physical memory and must address up to several GB of memory mapped I/O space.
Page 82: System Memory Address Space
System Firmware F_0000 C, D, and E 192K Segments C_0000 128K Memory A_0000 512K-640K Region 640K Intel® 460GX Chipset Software Developer’s Manual 16 MB High System Firmware FF00_0000 Processor 4 MB Specific Chipset 12 MB Specific FE00_0000 n x 32M...
Page 83: Low Extended Memory Region
The fixed gap is between 4 GB and (4 GB minus 32 MB) and is always enabled. This region must not be defined as WB. DRAM supported by the 460GX chipset that is masked by this hole is remapped to an area over 4 GB. The fixed gap is further divided into three regions: •...
Page 84: High Extended Memory (Above 4G)
4.1.4 High Extended Memory (above 4G) The entire address space above 4 GB is treated by the 460GX chipset as ordinary memory. The top of system memory is calculated by firmware. Processor accesses above the top of system memory are still claimed by the chipset, but are not forwarded to memory or PCI; instead they cause a BINIT#.
Page 85: I/O Address Map
FE00_0000 I/O Address Map The 460GX chipset allows I/O addresses to be mapped to resources supported on the I/O buses underneath the 460GX chipset controller. This I/O space is partitioned into sixteen 4K byte segments. Each of the segments can be individually configured to any I/O bus. Segment 0 is always assigned to the compatibility I/O bus (of which there is only one per system).
Page 86: System I/O Address Space
I/O writes are deferred. I/O reads are always deferred. Note, the 460GX chipset does not support ISA expansion aliasing. The IFB supports a full I/O space decode, so the compatibility issue will be drivers that rely on the I/O aliasing behavior.
Page 87: Devices View Of The System Memory Map
PCI buses in the system can no longer access the VGA range. Figure 4-4. System Memory Address Space as Viewed from an Expander Bridge (PXB/GXB) FFF_FFFF_FFFF 1_0000_0000 10_0000 F_0000 C_0000 A_0000 Intel® 460GX Chipset Software Developer’s Manual Top of Memory FFFF_FFFF System Memory High System Firmware FF00_0000...
Page 88: Legal And Illegal Address Disposition
Reads are sent to PCI-0a for master Transaction; write, PCI-0a abort. IB writes are turned to Reads sent to for read interrupts. OB writes get No-Data PCI 0a, writes response and are dropped dropped Intel® 460GX Chipset Software Developer’s Manual Dest. Decision...
Page 89 Note: The only ranges the PXB doesn’t claim are MMBASE to MMT, FEF0_0000h to FEFF_FFFFh, and 4G-16M to 4G. If the PCI card initiates a request to any other address, it will be sent up as TPA or memory. Intel® 460GX Chipset Software Developer’s Manual Outbound Inbound...
Page 90 System Address Map 4-10 Intel® 460GX Chipset Software Developer’s Manual...
Page 91: Memory Subsystem
Organization The 460GX chipset supports 1 or 2 memory cards. Each card supports up to 8 GB of memory using 128 MB DIMM’s (32 GB with 1 GB DIMM’s); 2 cards provide up to 16 GB of memory (64 GB with 1 GB DIMM’s).
Page 92: Maximum Memory Configuration Using Two Cards
1 of 4 x 72 x 72 x 72 x 72 Stack A row 4 of 4 Stack L memory card A Intel® 460GX Chipset Software Developer’s Manual MDb[71:0] 288 bits x 72 x 72 x 72 x 72 288 bits...
Page 93: Dimm Types
DIMMs may have a buffer on the DIMM itself. The buffer can be used in a registered mode or a pass-through mode. The 460GX will support both buffered and unbuffered DIMMs. It will support the buffered DIMM in the pass-through mode, not the registered mode. Thus the timings of the state machines in the MAC will be the same for both types of DIMM.
Page 94: Interleaving/Configurations
This lends itself well to designs which require a large memory system of many gigabytes. The 460GX will implement the second approach. It will attempt to increase the amount of parallelization. Addresses will be spread out across multiple rows and cards.
Page 95: Summary Of Configuration Rules
Performance will be optimal with evenly populated rows. Knowing that users may not populate the card optimally, the 460GX will attempt to spread addresses out as best it can in an unevenly populated system.
Page 96: Memory Subsystem Clocking
A row of memory may have a chip or DIMM fail. If an un-correctable error occurs, the system will machine-check, usually resulting in a reset. The 460GX will report which row failed. During the next re-boot or at power on, if the memory test fails, firmware may map the failing row as if it didn’t exist.
Page 97: Hardware Initialization
256 MB 512 MB 1 GB 2 GB 4 GB 8 GB 16 GB 32 GB 64 GB Intel® 460GX Chipset Software Developer’s Manual Time to Scrub 10 minutes 20 minutes 40 minutes 1.2 hours 3 hours 5 hours 10 hours 20 hours 1.6 days...
Page 98 Memory Subsystem Intel® 460GX Chipset Software Developer’s Manual...
Page 99: Data Integrity And Error Handling
If it is used, then the error is found at that point. The 460GX chipset will isolate the error reporting as close to the error itself as possible. In some cases this can be to a failing DRAM or PCI card. In others it will be for a PCI bus or Expander port.
Page 100: Dram
DRAM • The 460GX chipset provides ECC generation on all writes into the DRAM, and ECC checking on all reads from the DRAM. Single-bit errors are corrected. Multi-bit errors will return poisoned data. Both types of errors are logged, with the address and ECC bits for the data being recorded.
Page 101: Memory Ecc Routing
This allows software to poll periodically looking for single bit errors while not preventing other errors from being logged. Other than these two conditions, there should never be more than one bit set in any FERR. Intel® 460GX Chipset Software Developer’s Manual Data Integrity and Error Handling...
Page 102: Masked Bits
After software clears the NERR/FERR bit that caused the error, it will do an EOI to the PID to re- enable interrupt reporting by the PID. If INTREQ# is still active after the EOI, then a new interrupt is generated. Intel® 460GX Chipset Software Developer’s Manual...
Page 103: Xbinit
BINIT#. The exact cause must be read from the SDC. This is set for parity errors on the control interface between the SAC and SDC or for protocol errors. Intel® 460GX Chipset Software Developer’s Manual Data Integrity and Error Handling...
Page 104: System Bus Errors
SDC sends data to the MDC, it signals that it did so to the SAC. This error is flagged when the ‘data-sent’ signal is seen by the SAC, but there are no writes to that stack pending in the SAC. Intel® 460GX Chipset Software Developer’s Manual...
Page 105: Sac To Mac Interface Errors
‘Load’ overlapping ‘Load’. Set when the SDC is doing a ‘Load’ by receiving data and a second ‘Load’ is seen before the first ‘Load’ finishes. This implies the MDC is sending data for two different lines at the same time. Intel® 460GX Chipset Software Developer’s Manual Data Integrity and Error Handling...
Page 106: Sdc/System Bus Errors
The log register is updated when the appropriate bit is set in the status register. Only after the status register (FERR register) is cleared will a new value be captured on subsequent errors. Table 6-1 show which error occurred. Many of the errors also capture Intel® 460GX Chipset Software Developer’s Manual...
Page 107: Sac Address On An Error
Write ‘1’ to clear the SDC_FERR and SDC_NERR registers. Writing a ‘1’ to either register in the SDC will clear both the SDC_FERR and SDC_NERR at the same time. Intel® 460GX Chipset Software Developer’s Manual Data Integrity and Error Handling Table 6-1.
Page 108: Sdc Logging Registers
RAM contains the address of the transaction before it has been translated into a memory address. This address may have come from the system bus for a processor or a 460GX-initiated coherent access, or it may have come from AGP or other non-coherent source. The RAM/CAM may only be used for coherent transactions.
Page 109: Clearing Errors
Re-enable interrupts or other system signaling Multiple Errors With the number of errors that are detected in the 460GX chipset, there are many possible multiple error cases. There is no way to specify what can happen in the case of every combination. In general the first error that is found is the important one.
Page 110: Sdc Multiple Errors
| Store ITID in FSETID, log SNE in FERR | Store ITID in DEDTID, log SNE in FERR | Store ITID in FSETID, log only SNE in FERR | Store ITID in DEDTID, log only SNE in FERR Intel® 460GX Chipset Software Developer’s Manual...
Page 111: Sac Multiple Errors
The data from the processor for the IWB has a 2x error. Even though the processor data is not used, since the expander bustransaction was a full line write, the data will be sent to DRAM as poisoned. Intel® 460GX Chipset Software Developer’s Manual Data Integrity and Error Handling 6-13...
Page 112: Data Flow Errors
1Parity Generate parity as DP xor BE0 xor BE1, not 18-way XOR Expander: From xXB Expander: To xXB Intel® 460GX Chipset Software Developer’s Manual ITID Check parity. RETIREMENT Check parity. Pass data with good/bad parity to SDC or Expander (peer).
Page 113: Error Conditions
XBINIT#, and the interrupts there is a driver enable. If the driver is disabled, then these signals won’t be active, even if it says Unconditional in the table. Intel® 460GX Chipset Software Developer’s Manual Data Integrity and Error Handling From Processor Check parity, if bad poison ECC of chunk.
Page 114: Error Cases
FERR_SAC[SFE] SDC_FERR[IPE], FERR_SAC[SFE] SDC_FERR[RLE], DPBRLE_FERR, FERR_SAC[SFE] SDC_FERR[DPE], FERR_SAC[SNE] SDC_FERR[BPE], FERR_SAC[SNE] SDC_FERR[CIE], FERR_SAC[SFE] FERR_SAC[FRE] FERR_SAC[RPE] FERR_SAC[IPE] FERR_SAC[SCxx] FERR_SAC[AE] Intel® 460GX Chipset Software Developer’s Manual Qualifier Register SECF_D_FERR, SECF_ECC_FERR, Enable SECF_TXINFO_FERR, FSETID DEDF_D_FERR, DEDF_ECC_FERR, Enable DEDF_TXINFO_FERR, FSETID SECx_D_FERR, SCME SECx_ECC_FERR, Enable SECx_TXINFO_FERR,...
Page 115 ‘Forward’ ‘Forward’ Unconditional BINIT# overlapping ‘Load’ ‘Load’ overlapping Unconditional BINIT# ‘Load’ ‘Load’ overlapping Unconditional BINIT# ‘Forward’ ‘Forward’ Unconditional BINIT# Underflow Intel® 460GX Chipset Software Developer’s Manual System Status Action Register FERR_SAC[RQE] FERR_SAC[ASE] FERR_SAC[IHS] FERR_SAC[TE] SDC_FERR[FS0], FERR_SAC[SFE] SDC_FERR[FS2], FERR_SAC[SFE] SDC_FERR[FS1],...
Page 116 PCISTS[SSE] PCISTS[PE], PCISTS[DPE] if PERRE PCISTS [RMA], FERR_PCI PCISTS [RMA], FERR_PCI PCISTS [RMA] (FERR_PCI is not set) PCISTS [RTA], FERR_PCI FERR_GART Intel® 460GX Chipset Software Developer’s Manual Qualifier Register Nothing Nothing Nothing Nothing Nothing Nothing Nothing TXDERR _INTE, TXDERR...
Page 117 PERR# Asserted card Optionally turned to by Card SERR# by PXB. Intel® 460GX Chipset Software Developer’s Manual System Status Action Register FERR_GART FERR_GART FERR_GART FERR_PCI PCISTS [SSE],...
Page 118: Pci Integrity
PCISTS register’s Received Master Abort (RMA) bit. The PXB then has two options for generating a response. 6-20 System Status Action Register PCISTS[PE], PCISTS [SSE], ERRSTS[2] ERRSTS [5] ERRSTS[6], PCISTS[DPE] Intel® 460GX Chipset Software Developer’s Manual Qualifier Register Nothing SERRE Nothing Nothing...
Page 119: Pxb As Target
Refer to the PCI specification for a complete description of the required PCI protocol. 6.11.3 PXB as Target 6.11.3.1 Target Disconnect The PXB will issue a target disconnect under the following circumstances: Intel® 460GX Chipset Software Developer’s Manual Data Integrity and Error Handling 6-21...
Page 120: Gxb Error Flow
2 byte enables). At the top of the inbound queue, the data, BE and parity is sent to the Expander bus as-is out of the queue. There is no checking done in the GXB. If there is bad parity at the SAC, the SAC will flag the error. 6-22 Intel® 460GX Chipset Software Developer’s Manual...
Page 121 PCISTS Error Logged - Set when any error bit, except RMA (bit 13), in PCISTS is set. This includes bits 15, 12 or 8. Setting this bit in FERR_PCI does not cause an interrupt or BINIT#. Intel® 460GX Chipset Software Developer’s Manual Data Integrity and Error Handling Table 6-1 for the behavior of each error.
Page 122 PCI bus. The GXB will not report this error with either interrupt or BINIT#. The error is actually reported by the SAC or allowed to continue to memory where it will be poisoned. 6-24 Intel® 460GX Chipset Software Developer’s Manual...
Page 123: Gxb Error Flow
High Read Read Data Data Check Parity. If PCI, then corrupt outgoing parity. Intel® 460GX Chipset Software Developer’s Manual SAC Interconnect Check parity. On HDR: BINIT#. Drop Data PKT and data. Set FERR. Pass data to SAC with parity from queue, don’t check outgoing parity.
Page 124: Wxb Data Integrity And Error Handling
This allows better isolation of errors and possible recovery. Note: Multiple errors occurring in (nearly) the same cycle may result in multiple bits being set in the First Error register. 6-26 Intel® 460GX Chipset Software Developer’s Manual...
Page 125: Error Mask Bits
To obtain the listed escalation, the following settings are required: XBINITE=’0’’. 1. See Section 6.12.6 for a description of the P(A/B)INTRQ interrupt. Intel® 460GX Chipset Software Developer’s Manual Data Integrity and Error Handling Error interrupt. In the case of data parity errors, the minimal...
Page 126: Supported Error Escalation To Serr_Out
HPSERR, OSERR, DTE, APE, OPERR, HPPERR, PUIQ HPSERR, OSERR, DTE, FUIQ, PCIDPE HPSERR, OSERR, DTE, APE FUIQ, PCIDPE HPSERR, OSERR, DTE, FUIQ, PCIDPE, OPERR, HPPERR, PUIQ HPSERR, OSERR, DTE, APE FUIQ, PCIDPE, OPERR, HPPERR, PUIQ P(A/B)INTRQ# Intel® 460GX Chipset Software Developer’s Manual SERR_OUT# Escalation...
Page 127: Intrq# Interrupt
The single exception to this rule is Hard Fail Completion which will not initiate any sideband error signal (INTRQ#, SERR# or XBINIT#). However, an in-band PCI Target Abort will occur as a result of a Hard Fail Completion. Intel® 460GX Chipset Software Developer’s Manual Data Integrity and Error Handling Section .
Page 128: Error Conditions
PERR# during write data cycles. If a parity error is detected, and the PCICMD registers PERRE bit is set, then the PCISTS register’s Detected Parity Error 6-30 Intel® 460GX Chipset Software Developer’s Manual...
Page 129 The PCI specification identifies numerous cases that are violations of the PCI protocol. Other than the cases identified above, the WXB makes no attempt to check for such violations. Response to such violations is undefined. This includes, but is not limited to: Intel® 460GX Chipset Software Developer’s Manual Data Integrity and Error Handling 6-31...
Page 130 WXB. If the card doesn’t re-access the data in 2 error is flagged. 6-32 timer expires. The timer starts approximately when the data for a delayed Intel® 460GX Chipset Software Developer’s Manual PCI clocks, then an...
Page 131: Agp Subsystem
There is also an extension called AGP 4X mode, which has a bandwidth of 1 GB/s. AGP 2X mode cards will work in an AGP 4X mode slot. The 460GX chipset is designed to work at the AGP 4X mode bandwidths. It will support 3.3V AGP 1X and 2X mode cards as well.
Page 132: Gart Table Usage For 4K
GART Entry (16b if256 MB of GART space) GART Table Offset 14 Bit GART Entry 8b if 1 GB GART 6b if 256 MB GART GART Table Intel® 460GX Chipset Software Developer’s Manual 36b Main Memory Address 36b Main Memory Address...
Page 133: Gart Implementation
SRAM. Of course, in this case, there is no translation so the AGP card must put out the physical memory address itself. Intel® 460GX Chipset Software Developer’s Manual Figure 7-4 show the format of a GART entry. Accesses which hit a GART...
Page 134: Programming Gart
GART, thus lowering system cost. The GXB will support 4 MB pages. Using 4 MB pages, 256kB of SRAM could provide 256 GB of AGP space. The 460GX chipset will not support more than 32 GB of translatable graphics space. 7.1.1.2 GTLB The GXB does not implement any GTLB or hold any old translations.
Page 135: Gart Implementation
Or the application may know that the data in memory was not used by the processor (e.g. it came from disk) and wants the graphics card to fetch the data without using address bus bandwidth, so forces the access to be non-coherent. Intel® 460GX Chipset Software Developer’s Manual 25ns 50ns...
Page 136: Interrupt Handling
This address range lies outside the physical memory space. It also lies outside the range of addresses mapped to I/O. This range may exist in one of two places in the 460GX chipset system map. The virtual address is limited to 40 bits for the GXB, even when in 64-bit addressing mode.
Page 137: Traffic Priority
DRAM location. PCI-space is an address that would normally be directed to a PXB and a PCI device. Both the DRAM-space and the PCI-space lie outside the AGP-space. These areas must not overlap. The destination of the request is determined by address registers in configuration space. Intel® 460GX Chipset Software Developer’s Manual AGP Subsystem...
Page 138: Ordering Rules
Note: Accesses from an AGP card that are directed to a PCI bus are a system fault and cause a BINIT# (system reboot). The 460GX chipset does NOT support any access originating from the AGP port to another PCI bus. This is true for PCI cycles (FRAME# active) as well as AGP cycles.
Page 139: Address Alignment And Transfer Sizes
Retry, and completing the request without holding the master in wait-states is called a Delayed Transaction. The GXB will delay all memory space read requests (unless a delayed slot is unavailable); no other request types are delayed. Intel® 460GX Chipset Software Developer’s Manual AGP Subsystem...
Page 140 PCI master by using information that was latched into the target during the initial request. This information consists of the address, command and byte enables. which read request information is used for matching Delayed Read Completions to the requesting agent. 7-10 Table 7-2 Intel® 460GX Chipset Software Developer’s Manual illustrates...
Page 141: Delayed Read Matching Criteria
7.2.7.7 Inbound I/O Writes I/O writes on the PCI bus are not claimed by the GXB. Intel® 460GX Chipset Software Developer’s Manual Address Match Match PCI clock timer is started as described in the PCI 2.2 Accumulates posted data until (a) a cache line boundary is reached, or (b) the master disconnects, before forwarding the request to the SAC.
Page 142 GXB must terminate and switch to using the Memory Write command. 7-12 Table Table 7-4 shows some write combining examples. Intel® 460GX Chipset Software Developer’s Manual 7-3.
Page 143: Bandwidth
50/50 mix of reads by the graphics card and writes by the processor to the card. This table will change as the implementation is completed and should be viewed as a guideline for the graphics card designer for relative performance trade-offs. Intel® 460GX Chipset Software Developer’s Manual Transfer Data Length Mode <...
Page 144: Inbound Read Prefetching
AGP peak, so there is no extra bandwidth in case the bridge prefetched the wrong data. For this reason, the 460GX chipset will have no prefetching of graphics data. The graphics card should have enough buffering and outstanding transactions to keep its pipes full. With pipelining, the card can fetch the data it needs in advance of using it.
Page 145 In a MARG with DRAM accesses disabled (the MARGs cover the C, D, E, and F segments). • In the VGA region (A_0000-BFFFF) with VGAGE enabled so that this region is directed to PCI, a PCI access in this range would not have gotten DEVSEL#. Intel® 460GX Chipset Software Developer’s Manual AGP Subsystem 7-15...
Page 146 AGP Subsystem 7-16 Intel® 460GX Chipset Software Developer’s Manual...
Page 147: Wxb Hot-Plug
Configuration registers are not described here when implemented exactly as described in the PCI Specification 2.2. The following map shows registers specific to the IHPC. WXB Integrated Hot-Plug controller derived from technology licensed from Compaq Corporation. Intel® 460GX Chipset Software Developer’s Manual Controllers (IHPCs). The A-side...
Page 148: Ihpc Configuration Register Space
Memory Mapped Register Access Port NOTE: The first 64 bytes are predefined in the PCI specification. All other locations are defined specifically for the component of interest. SVID Interrupt Line Switch Change SERR status Intel® 460GX Chipset Software Developer’s Manual...
Page 149: Page Number List For The Ihpc Pci Register Descriptions
PCI device. Writes to this register have no effect. Bits Description 15:0 Vendor Identification Number This is a 16-bit value assigned to Intel. Intel VID = 8086h 8.1.3 DID: Device Identification Register Address Offset: Default Value: This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device.
Page 150: Pcicmd: Pci Command Register
This bit is configurable in the IHPC with the default value of zero (0). I/O Space This bit controls a device’s response to I/O space accesses. The IHPC does not respond to I/O space accesses. Hardwired Value = 0. 04h-05h Size: 0000h Attribute: Intel® 460GX Chipset Software Developer’s Manual 16 bits Partial Read/Write...
Page 151: Pcists: Pci Status Register
RID: Revision Identification Register Address Offset: Default Value: This register contains the revision number of the IHPC. These bits are read-only and writes to this register have no effect. Intel® 460GX Chipset Software Developer’s Manual 06h – 07h Size: 0200h Attribute:...
Page 152: Class: Class Register
Hardwired Value = 00h Hardwired Value = 01h 09 – 0Bh Size: 080400h Attribute: Size: Attribute: Size: Attribute: Size: Attribute: Intel® 460GX Chipset Software Developer’s Manual 24 bits Read-Only 8 bits Read/Write 8 bits Read/Write 8 bits Read-Only...
Page 153: Base Address
See PCI Specification, Revision 2.2. 8.1.13 SID: Subsystem ID Address Offset: Default Value: See PCI Specification, Revision 2.2. 8.1.14 Interrupt Line Address Offset: Default Value: Intel® 460GX Chipset Software Developer’s Manual 10h-13h Size: 00000000h Attribute: 2Ch –2Dh Size: 0000h Attributes: 2Eh - 2Fh...
Page 154: Interrupt Pin
1. Bit 0 may be changed to a 1 after Reset in future implementation. 40h-41h 0000h 42h-43h Size: 0002h Attribute: Intel® 460GX Chipset Software Developer’s Manual Size: 8 bits Attribute: Read Only Size: 16 bits Attribute:...
Page 155: Hot-Plug Features
Slot F is MSB. Slot A is LSB. These bits can be cleared by writing a logic 1 to the appropriate position. This register does not effect PCI interrupts. Intel® 460GX Chipset Software Developer’s Manual 44h-45 Size:...
Page 156: Arbiter Serr Status
Register in IHPC configuration space. The default power-up value is included in each register description heading. 8-10 Size: Attribute: 50h-53h Size: 00000000h Attribute: 54h-57h Size: 00000000h Attribute: Intel® 460GX Chipset Software Developer’s Manual 8 bits Partial Read/Write 32 bits Partial Read/Write 32 bits Read/Write...
Page 157: Ihpc Memor Mapped Register Space
(RW) Extended Hot-Plug Misc. (RW) NOTE: The first 64 bytes are predefined in the PCI specification. All other locations are defined specifically for the component of interest. Intel® 460GX Chipset Software Developer’s Manual Switches Switch Mask Serial Input Data (RO)
Page 158: Page Number List For Ihpc Memory Mapped Register Descriptions
When 1, Slot B is powered and connected to the PCI bus Enable Slot A When 1, Slot A is powered and connected to the PCI bus 8-12 Size: 8 bits Attribute: Partial Read/Write (Pwr Good Rst Only) Intel® 460GX Chipset Software Developer’s Manual Page...
Page 159: Hot-Plug Miscellaneous
LEDs for that slot. It is intended that the green LED is a power indicator and the amber LED is the attention indicator.Following chip power on, all LED bits will be cleared Intel® 460GX Chipset Software Developer’s Manual 02h - 03h...
Page 160: Hot-Plug Interrupt Input And Clear
(either high to low or low to high), and the bit is not masked in the Interrupt Mask register, an interrupt is generated and the state of that input is latched 8-14 Size: Varies Attribute: Intel® 460GX Chipset Software Developer’s Manual 32 bits Read/Write Clear (Pwr Gd Rst Only)
Page 161: Hot-Plug Interrupt Mask
Clear Register) bits. If a state change occurs on an input while the mask bit for that input is set to one, then no interrupt will be generated for that state change. If the mask bit is cleared, then an interrupt will be generated on the next state change. Intel® 460GX Chipset Software Developer’s Manual Size: FFFFFFFFh...
Page 162: Serial Input Byte Data
Input Data Register. The contents will be a copy of the corresponding byte in the Interrupting Input and Clear Register (least significant) or Non-Interrupting Inputs Register (most significant). Bits Description Serial Input Data Register. RO 8-16 Size: Attribute: Intel® 460GX Chipset Software Developer’s Manual 8 bits Read-Only (Pwr Good Rst Only)
Page 163: Serial Input Byte Pointer
Slot A M66EN, PCI 66 MHz Clock Enable 8.2.11 Hot-Plug Slot Identifier Address Offset: Default Value: This register is a copy of Configuration Register 40h, byte 0. Intel® 460GX Chipset Software Developer’s Manual Size: Attribute: Size: Attribute: 0000h WXB Hot-Plug...
Page 164: Hot-Plug Switch Interrupt Redirect Enable
Address Offset: Default Value: Bits Description 15:0 reserved (0) 8-18 Size: Sampled at PWRGD Attribute: Read/Write (Pwr Good Rst Only) 0000h Intel® 460GX Chipset Software Developer’s Manual Size: 8 bits Attribute: Read/Write 8 bits Size: 16 bits Attribute: Partial Read/Write...
Page 165: Ifb Register Mapping
9.1.1 PCI Configuration Registers (Function 0) Table 9-1. PCI Configuration Registers–Function 0(PCI to LPC/FWH Interface Bridge) Configuration Offset 00–01h 02–03h 04–05h Intel® 460GX Chipset Software Developer’s Manual Mnemonic Register Vendor Identification Device Identification PCICMD PCI Command Register Access...
Page 166 LPC Sound Decode FWHDE Firmware Hub Decode Enable LPCGD LPC Generic Decode Range LPCDE LPC Decode Enables FWHS Firmware Hub Select – Reserved Intel® 460GX Chipset Software Developer’s Manual Register Access – – – – – – – – –...
Page 167: Ide Configuration
00–01h 02–03h 04–05h 06–07h 09-0Bh 0F–1Fh 20–23h 24–3Fh 40–43h 45–47h 4A–4Bh 4C–F7h F8-FBh FC-FFh Intel® 460GX Chipset Software Developer’s Manual Mnemonic Register Vendor Identification Device Identification PCICMD PCI Command PCISTS PCI Device Status Revision Identification CLASSC Class Code – Reserved...
Page 168: Universal Serial Bus (Usb) Configuration
Reserved LEGSUP USB Legacy Keyboard/Mouse Control Reserved USBRES USB Resume Enable – Reserved – Reserved – Manufacturer’s ID Register – Reserved Intel® 460GX Chipset Software Developer’s Manual Register Access – – – – – – ----- – – – –...
Page 169: Smbus Controller Configuration
Configuration Offset 00–01h 02–03h 04–05h 06–07h 09-0Bh 0C-1Fh 20-23h 24-3Bh 3E-3Fh 41-F3h F4-F7h F8-FBh FC-FFh Intel® 460GX Chipset Software Developer’s Manual Mnemonic Register Vendor Identification Device Identification PCICMD PCI Command PCISTS PCI Device Status Revision Identification CLASSC Class Code – Reserved Base Address Register –...
Page 170 IFB Register Mapping Intel® 460GX Chipset Software Developer’s Manual...
Page 171: Ifb Usage Considerations
Plug and Play motherboard resources with the Device ID of PNP0C02. If the ACPI tables are used instead of the PNP Device node entries for reporting resources the change has to be incorporated Intel® 460GX Chipset Software Developer’s Manual 10-1...
Page 172: Ultra Dma Configuration
Reserved Ultra DMA Cycle Time (PCT1) 00: CT=4 clks, RP=6 clks 01: CT=3 clks, RP=5 clks 10: CT=2 clks, RP=4 clks 11: Reserved Intel® 460GX Chipset Software Developer’s Manual Secondary Primary Primary Drive 0 Drive 1 Drive 0 Ultra DMA...
Page 173: Determining A Drive's Transfer Rate Capabilities
Capability Device Type Device Type Ultra DMA Ultra DMA Ultra DMA Ultra DMA PIO, DMA Intel® 460GX Chipset Software Developer’s Manual Word Bits Offset Fields that Indicate Device Type General Configuration: 0: ATA Device 1: ATAPI Device Fields that Indicate Ultra DMA Drive Capabilities...
Page 174 1: the fields reported in word 64-70 are valid Advanced Flow Control PIO Transfer Modes Supported bit 0: PIO3 (w/IORDY Flow Control) bit 1: PIO4 (w/IORDY Flow Control) 15:0 Minimum PIO Transfer Cycle Time with IORDY Flow Control Intel® 460GX Chipset Software Developer’s Manual Field...
Page 175: Determining A Drive's Best Ultra Dma Capability
Software should initially determine a drive’s best Mult Word DMA capability initially. If a drive doesn’t support multi word DMA Modes 0 or 1, then software should check if single word DMA Mode 2 is supported. Intel® 460GX Chipset Software Developer’s Manual Word Bits...
Page 176: Identify Device Information Used For Determining Multi/Single Word Dma Drive Capabilities
0: Multi Word DMA Mode 1 is not supported bit 0: 1: Multi Word DMA Mode 0 is supported 0: Multi Word DMA Mode 0 is not supported 15:0 Minimum Multi Word DMA Transfer Cycle Time per Word Table Intel® 460GX Chipset Software Developer’s Manual Field 10-4.
Page 177: Drive Multi Word Dma/Single Word Dma Capability As A Function Of Cycle Time
• PIO2 w/IORDY • PIO2 (without IORDY) • Compatible (Drive does not support any of the above PIO Modes.) Intel® 460GX Chipset Software Developer’s Manual IFB Usage Considerations Drives Reported DMA Drive’s Best DMA Mode Cycle Time t <= 120ns Multi Word DMA Mode 2 120 <...
Page 178: Identify Device Information Used For Determining Pio Drive Capabilities
180 < t <= 240ns t > 240ns t <= 180ns 180 < t <= 240ns t > 240ns N/A (drive must support t<= 240ns) Intel® 460GX Chipset Software Developer’s Manual Field Drive’s Best PIO Mode PIO4 PIO3 PIO2 PIO0/Compatible...
Page 179: Ifb Timing Settings
(w/IORDY) a. Configurations where a drive reports a PIO speed much slower than its reported DMA speed require the DMA Timing Enable Only Select bit to be Enabled. Intel® 460GX Chipset Software Developer’s Manual Fast PIO Non Ultra DMA Supported?
Page 180: Ide Mode/Drive Feature Settings For Optimal Dma/Pio Operation
(if fixed disk) Disabled Disabled Depends Enabled on Drive (if fixed disk) Disabled Disabled Depends Enabled on Drive (if fixed disk) Intel® 460GX Chipset Software Developer’s Manual Slave IDE Timing Register IORDY Fast Value Timing Sample Timing (hex) Register Register...
Page 181: Drive Configuration For Selected Timings
Once the IFB Timing Modes for DMA, PIO and Ultra DMA have been selected, the Set Features Command (0 x EF) with Set Transfer Mode (subcommand 0 x 03) can be issued to set the drives on the system to the optimal speeds: Intel® 460GX Chipset Software Developer’s Manual IDETIMx IDETIMx...
Page 182: Ultra Dma/Multi Word Dma/Single Word Transfer/Mode Values
Single Word DMA Mode Single Word DMA Mode Disabled ATA SET_FEATURES -Command Set Transfer Mode Sub Command Parameter for Selected Speed Intel® 460GX Chipset Software Developer’s Manual ATA SET_FEATURES - Command Set Transfer Mode Sub Command Parameter for Selected Speed...
Page 183: Settings Checklist
Primary Master Drive 1 Primary Slave Drive 2 Secondary Master Drive 3 Secondary Slave Intel® 460GX Chipset Software Developer’s Manual Drive 0 DMA Reserved Capable (DMACAP0) 0: Drive is PIO only. 1: Drive is capable and configured for DMA transfers.
Page 184: Example Configurations
20-23h system dependent 40-41h A307h 42-43h A303h 4A-4Bh 0102h Intel® 460GX Chipset Software Developer’s Manual Comments Ensure that bits 0 and 2 are ‘1’ Ensure that bit 0 (of register value) is ‘1’ Non Ultra DMA Fast PIO Supported? Supported?
Page 185 Drive 0 Fixed Disk Primary Master Drive 1 Fixed Disk Primary Slave Drive 2 ATAPI Secondary CDROM Single Intel® 460GX Chipset Software Developer’s Manual Best IFB Ultra Ultra Best DMA Best PIO Mode Mode Mode Multi Word PIO4 Ultra DMA Mode...
Page 186: Ultra Dma System Software Considerations
System dependent 40-41h E377h 42-43h A103h 4A-4Bh 0000h Intel® 460GX Chipset Software Developer’s Manual Comments Ensure that bits 0 and 2 are ‘1’. Ensure that bit 0 (of register value) is ‘1’. Mode config. for Primary Mode config. for Secondary...
Page 187: Additional Ultra Dma/Pci Bus Master Ide Device Driver Considerations
10.5.11.1 Bus Master IDE Command and Status Register 10.5.11.2 BMICX–Bus Master IDE Command Register (I/O) Address Offset: Default Value: Attribute: Intel® 460GX Chipset Software Developer’s Manual Primary Channel–Base + 00h; Secondary Channel–Base + 08h Read/Write IFB Usage Considerations 10-17...
Page 188 When this bit is read as a zero, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 10-18 Primary Channel–Base + 02h; Secondary Channel–Base + 0Ah Read/Write Clear Intel® 460GX Chipset Software Developer’s Manual...
Page 189: Usb Resume Enable Bit
For performing legacy power management, the firmware has to set these two bits in each of the functions, if it wants the USB Host controller to monitor these ports. Intel® 460GX Chipset Software Developer’s Manual Description DMA transfer is in progress. No interrupt has been generated by the IDE device.
Page 190 IFB Usage Considerations 10-20 Intel® 460GX Chipset Software Developer’s Manual...
Page 191: Lpc/Fwh Interface Configuration
The VID Register contains the vendor identification number. This register, along with the Device Identification Register, uniquely identifies any PCI device. Writes to this register have no effect. 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. 11.1.2 DID–Device Identification Register (Function 0)
Page 192: Pcicmd-Pci Command Register (Function 0)
DEVSEL# Timing Status (DEVT)–RO. The IFB always generates DEVSEL# with medium timing for Function 0 I/O cycles. Thus, DEVT=01. This DEVSEL# timing does not include Configuration cycles. 11-2 04–05h 0007h Read/Write Description 06–07h 0280h Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 193: Rid-Revision Identification Register (Function 0)
HEDT–Header Type Register (Function 0) Address Offset: Default Value: Attribute: The HEDT Register identifies the IFB as a multi-Function device. Device Type (DEVICET). 80h=multi-Function device. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration Description Stepping Dependent Read Only Description...
Page 194: Acpi Base Address (Function 0)
SERIRQ frame entry is blocked. This interrupt can be shared with a PCI interrupt. 11-4 40-43h 00000001h Read/Write Description Read/Write Description Read/Write Description Bits Intel® 460GX Chipset Software Developer’s Manual SCI Map IRQ9 FEMPTY# IRQ8 IRQ0 IRQ10 IRQ11 Reserved...
Page 195: Biosen-Bios Enable Register (Function 0)
Interrupt Routing. When bit 7=0, this field selects the routing of the PIRQx to one of the interrupt controller interrupt inputs. Bits[3:0] 0000 0001 0010 0011 0100 0101 Intel® 460GX Chipset Software Developer’s Manual 4E-4Fh 07C1h Read/Write Description Description IRQ Routing Bits[3:0] IRQ Routing...
Page 196: Serirqc-Serial Irq Control Register (Function 0)
8 Mbyte 3 Mbyte 1000 9 Mbyte 4 Mbyte 1001 10 Mbyte 5 Mbyte 1010 11 Mbyte 6 Mbyte Intel® 460GX Chipset Software Developer’s Manual Bits[7:4] Top of Memory 1011 12 Mbyte 1100 13 Mbyte 1101 14 Mbyte 1110 15 Mbyte...
Page 197: Mstat-Miscellaneous Status Register (Function 0)
Delayed Transaction Enable. When this bit is a “1”, it enables the Delayed Transaction mechanism when the IFB is the target of a PCI transaction. When this bit is a “0”, the Delayed Transaction mechanism is disabled. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration 6A–6Bh...
Page 198: Mgpioc–Muxed Gpio Control (Function 0)
Reserved. Must be set to ‘11’. 11.1.19 DDMABP–Distributed DMA Slave Base Pointer Registers (Function 0) Address Offset: Default Value: Attribute: 11-8 84-85h 0500h Read/Write Description 90-91h 0000h Read/Write Description 92-93h (CH0-3), 94-95h (CH5-7) 0000h Read/Write Intel® 460GX Chipset Software Developer’s Manual...
Page 199: Rtccfg-Real Time Clock Configuration Register (Function 0)
Upper RAM Enable: 0 = Accesses to RTC Upper 128 byte extended bank at I/O address 72- 73h is disabled. 1 = Accesses to 72-73h are forwarded to RTC Upper 128 byte extended bank. Reserved. Intel® 460GX Chipset Software Developer’s Manual Channel Description Read/Write...
Page 200: Gpio Base Address (Function 0)
Decode Range 3F8 - 3FF (COM 1) 2F8 - 2FF (COM 2) 220 - 227 228 - 22F 238 - 23F 2E8 - 2EF (COM 4) 338 - 33F 3E8 - 3EF (COM 3) Intel® 460GX Chipset Software Developer’s Manual...
Page 201: Lpc Fdd/Lpt Decode Ranges (Function 0)
Decode Range: The following table describes which range to decode for the FDD Port Reserved. Decode Range: The following table describes which range to decode for the LPT Port Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration Description Bits...
Page 202: Lpc Sound Decode Ranges (Function 0)
E80 - E87 F40 - F47 Bits Decode Range 330 - 331 300 - 301 Bits Decode Range 220 - 233 240 - 253 260 - 273 280 - 293 E4-E5h 0000h Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 203: Lpc Enables (Function 0)
E3H are cleared to ‘0’. If the pin is sampled as a logic ‘0’, then the firmware does exist, and all the bits in E3H are set to ‘1’. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration...
Page 204 3 MB (FFD00000H) to 4 GB - 2.5 MB (FFD7FFFFH) as well as register space starting at (4 GB- 4MB) - 3.0MB (FF900000h) to (4 GB-4MB) - 2.5MB (FF97FFFFh). The enable for this range is controlled through bit 2 of the FWH Decode Enable Register at E3H. 11-14 Description 00112233H Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 205: Pci To Lpc I/O Space Registers
Reserved. Must be 0. DMA Group Arbitration Priority. 1=Rotating priority; 0=Fixed priority Reserved. Must be 0 DMA Channel Group Enable. 1=Disable; 0 = Enable. Reserved. Must be 0. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration Description FC-FFh 00000000h...
Page 206 10 Channel 2 (6) 11 Channel 3 (7) 11-16 Channels 0-3=0Bh; Channels 4-7=0D6h Bits[7:2]=0; Bits[1:0]=undefined (CPURST or Master Clear) Write Only Description Channels 0-3–09h; Channels 4-7–0D2h Bits[1:0]=undefined; Bits[7:2]=0 (CPURST or Master Clear) Write Only Description Intel® 460GX Chipset Software Developer’s Manual...
Page 207 DREQ(s). Bit Channel 0 0 (4) 1 1 (5) 2 2 (6) 3 3 (7) Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration Channels 0-3–0Ah; Channels 4-7–0D4h Bits[1:0]=undefined; Bit 2=1; Bits[7:3]=0 (CPURST or a Master Clear) Write Only Description Channels 0-3–0Fh;...
Page 208 Read Only Description DMA Channel 0–000h DMA Channel 1–002h DMA Channel 2–004h DMA Channel 3–006h Undefined (CPURST or Master Clear) Read/Write Description Intel® 460GX Chipset Software Developer’s Manual DMA Channel 4–0C0h DMA Channel 5–0C4h DMA Channel 6–0C8h DMA Channel 7–0CCh...
Page 209 The Clear Byte Pointer Command (or CPURST or the Master Clear Command) clears the internal latch used to address the upper or lower byte of the 16-bit Address and Word Count Registers. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration DMA Channel 0–001h DMA Channel 1–003h...
Page 210: Interrupt Controller Registers
4. Special Mask Mode is cleared and Status Read is set to IRR. 11-20 Description Channel 0-3–00Dh; Channel 4-7–0DAh All bits undefined Write Only Description Channel 0-3–00Eh; Channel 4-7–0DCh All bits undefined Write Only Description INT CNTRL-1–020h; INT CNTRL-2–0A0h All bits undefined Write Only Intel® 460GX Chipset Software Developer’s Manual...
Page 211 Reserved. Must be programmed to all 0s. Cascaded Mode Enable. This bit must be programmed to 1 selecting cascade mode. Reserved. Must be programmed to all 0s. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration Description INT CNTRL-1–021h; INT CNTRL-2–0A1h...
Page 212 AEOI (Automatic End of Interrupt). This bit should normally be programmed to 0. This is the normal end of interrupt. If this bit is 1, the automatic end of interrupt mode is programmed. Microprocessor Mode. Must be programmed to 1 indicating an Intel Architecture-based system.
Page 213 Special Mask Mode (SMM). If ESMM=1 and SMM=1, the interrupt controller enters Special Mask Mode. If ESMM=1 and SMM=0, the interrupt controller is in normal mask mode. When ESMM=0, SMM has no effect. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration Description INT CNTRL-1–020h;...
Page 214 IRQ4 ECL. 0 = Edge Triggered mode; 1 = Level Triggered mode. IRQ3 ECL. 0 = Edge Triggered mode; 1 = Level Triggered mode. Reserved. Must be 0. 11-24 Description INT CNTRL-1–4D0h Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 215: Counter/Timer Registers
101 5 Hardware triggered strobe Binary/BCD Countdown Select. 0=Binary countdown. The largest possible binary count is . 1=Binary coded decimal (BCD) count is used. The largest BCD count allowed is 10 Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration INT CNTRL-2–4D1h...
Page 216 The two bytes do not have to be read successively (read, write, or programming operations for other counters may be inserted between the reads). Note that the Timer Counter 11-26 Description Description Intel® 460GX Chipset Software Developer’s Manual...
Page 217 Interval Counter Control Register. The counter I/O port is also used to read the current count from the Count Register and return counter programming status following a Read Back Command. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration Counter 0–040h; Counter 1–041h; Counter 2–042h Bits[6:0]=X;...
Page 218: Nmi Registers
IFB (see MSTAT Register description, 6Ah-6Bh, Function 0). Speaker Data Enable–R/W. 0=SPKR output is 0; 1= the SPKR output is the Counter 2 OUT signal value. Timer Counter 2 Enable–R/W. 0=Disable; 1=Enable. 11-28 061h Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 219: Real Time Clock Registers
The data port for accesses to the RTC standard RAM bank. Standard RAM Data Port. Data written to standard RAM bank address selected via RTC Index Register (070h). Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration 070h Bit[6:0]=undefined; Bit 7=1...
Page 220: Advanced Power Management (Apm) Registers
In addition, writes generate an SMI, if the APMC_EN bit (PCI Function 3, offset58h, bit 25) is set to 1. Reads do not generate an SMI. 11-30 072h Unknown Write Only Description 073h Unknown Read/Write Description 0B2h Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 221: Acpi Registers
SCI handler. Firmware has a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit. The SCI handler should then clear this bit by writing a 1 to it. Reserved. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration 0B3h...
Page 222 11-32 Description 02-03h Read/Write Bit 10: Undefined, All other bits ‘0’ 16 bits Description 04-05h Read/Write Bits 12:10 Undefined, All other bits ‘0’ 16 bits Description Intel® 460GX Chipset Software Developer’s Manual bit of the...
Page 223 When any bit is set in this register, and the corresponding bit is enabled in the General Purpose 0 Enable register, an SCI and a wake event will be generated. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration Description Mode Typically mapped to S1 state.
Page 224 USB, after power failure (RSMRST# low). This bit is automatically set to 0 if a Power Button Override occurs. Upon power up, this bit is undefined. Reserved. 11-34 Description OE-0Fh Read/Write 0000h 16 bits Description Intel® 460GX Chipset Software Developer’s Manual...
Page 225: Smi Registers
SMI# logic. These I/O registers are added to the end of the I/O register space defined by the ACPI block. All reserved bits will always return 0 when read, and will have no effect when written. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration...
Page 226 SMI_EN bit. This bit is reset by a PCI reset event. 11-36 1A-1Bh Read/Write Bits 8 Undefined, Bit 3 ‘1’, All other bits ‘0’ 16 bits Description Intel® 460GX Chipset Software Developer’s Manual...
Page 227: General Purpose I/O Registers
1. 11.2.9 General Purpose I/O Registers For the following GPIO Registers, bits 28:16 refer to the Muxed GPIO signals, and bits 8:0 refer to the dedicated GPIO signal. Intel® 460GX Chipset Software Developer’s Manual 1Ch-1Dh Read/Write 0000h 16 bits...
Page 228 GP Lock bit is set. The value of this bit only has meaning if the muxed GPIO is enabled as a GPIO. 23:20 Reserved. 11-38 GPIO GPIO[19] GPIO[18] Reserved Reserved Reserved Reserved GPIO[13] GPIO[12] GPIO[11] GPIO[10] 00-03h Read/Write 00000000h 32 bits Description 04-07h Read/Write 00000000h 32 bits Description Intel® 460GX Chipset Software Developer’s Manual GPIO GPIO[5] GPIO[4] GPIO[3] GPIO[2] GPIO[1] GPIO[0]...
Page 229 The value of the pin is determined by XORing the data bit with the invert bit. The setting of this bit has no effect if the pin is programmed as an input. This bit cannot be changed once the GP Lock bit is set. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration Description...
Page 230 This bit cannot be changed once the GP Lock bit is set. 11-40 0C-0Fh Read/Write 00000000h 32 bits Description 10-13h Read/Write 00000000h 32 bits Description 14-17h Read/Write 00000000h 32 bits Description Intel® 460GX Chipset Software Developer’s Manual...
Page 231 Pull-up: When set, an internal pull-up will be enabled on the pin. When disabled, the pull-up is disabled. This bit cannot be changed once the GP Lock bit is set. Intel® 460GX Chipset Software Developer’s Manual LPC/FWH Interface Configuration 1C-1Fh...
Page 232 LPC/FWH Interface Configuration 11-42 Intel® 460GX Chipset Software Developer’s Manual...
Page 233: Ide Configuration
IDE Controller Register Descriptions (PCI Function 1) This section describes in detail the registers associated with the IFB IDE Controller Function. This includes Programmed I/O (PIO), Bus Master, and “Ultra DMA/33” synchronous DMA Functionality. Intel® 460GX Chipset Software Developer’s Manual Mnemonic Register Vendor Identification...
Page 234: Vid-Vendor Identification Register (Function 1)
The VID Register contains the vendor identification number. This register, along with the Device Identification Register, uniquely identifies any PCI device. Writes to this register have no effect. 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel 12.2.2 DID–Device Identification Register (Function 1)
Page 235: Pcists-Pci Device Status Register (Function 1)
IFB PCI Function 1. 23:16 Base Class Code (BASEC). 01h=Mass storage device. 15:8 Sub-Class Code (SCC). 01h=IDE controller. Programming Interface (PI). 80h=Capable of IDE bus master operation. Intel® 460GX Chipset Software Developer’s Manual 06–07h 0280h Read/Write Description 09-0Bh 010180h...
Page 236: Mlt-Master Latency Timer Register (Function 1)
Bus Master interface registers and correspond to AD[15:4]. Reserved. Resource Type Indicator (RTE)–RO. This bit is hardwired to 1 indicating that the base address field in this register maps to I/O space. 12-4 Read/Write Description 20–23h 00000001h Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 237: Svid-Subsystem Vendor Id (Function 1)
IORDY Sample Point (ISP). This field selects the number of PCI clocks between IOR#/IOW# assertion and the first IORDY sample point. Bits[13:12] Number of Clocks 00 5 01 4 10 3 11 2 11:10 Reserved. Intel® 460GX Chipset Software Developer’s Manual 2C-2Dh 0000h Read only Description 2E-2Fh 0000h Read only Description 40–41h = Primary Channel 42–43h = Secondary Channel...
Page 238: Sidetim–Slave Ide Timing Register (Function 1)
IDE channel. This allows for programming of independent operating modes for each IDE agent. This register has no affect unless the SITRE bit is enabled in the IDETIM Register. 12-6 Description Read/Write only Intel® 460GX Chipset Software Developer’s Manual...
Page 239: Dmactl-Synchronous Dma Control Register (Function 1)
Primary Drive 1 SDMA Enable (PSDE1). 1 = Enable Synchronous DMA mode for primary channel drive 1. 0 = Disable (default). Primary Drive 0 SDMA Enable (PSDE0). 1 = Enable Synchronous DMA mode for primary channel drive 0. 0 = Disable (default). Intel® 460GX Chipset Software Developer’s Manual Description Read/Write Description...
Page 240: Sdmatim-Synchronous Dma Timing Register (Function 1)
00: CT = 4 PCICLK, RP = 6 PCICLK 01: CT = 3 PCICLK, RP = 5 PCICLK 10: CT = 2 PCICLK, RP = 4 PCICLK 11: Reserved 12-8 4A-4Bh 0000h Read/Write only Description Intel® 460GX Chipset Software Developer’s Manual...
Page 241: Ide Controller I/O Space Registers
This register enables/disables bus master capability for the IDE Function and provides direction control for the IDE DMA transfers. This register also provides bits that software uses to indicate DMA capability of the IDE device. Intel® 460GX Chipset Software Developer’s Manual Ultra DMA/33 Timing Modes Mode 0 (120 ns)
Page 242: Bmisx-Bus Master Ide Status Register (I/O)
0 of the BMICx Register is set to 0. When this bit is read as a zero, all data transferred from the drive during the previous bus master command is visible in system memory, unless the bus master command was aborted. 12-10 Description Primary Channel–Base + 02h; Secondary Channel–Base + 0Ah Read/Write Clear Description Intel® 460GX Chipset Software Developer’s Manual...
Page 243: Bmidtpx-Bus Master Ide Descriptor Table Pointer Register (I/O)
31:2 Descriptor Table Base Address (DTBA). Bits [31:2] correspond to A[31:2]. Reserved. Intel® 460GX Chipset Software Developer’s Manual Description DMA transfer is in progress. No interrupt has been generated by the IDE device. The IDE device generated an interrupt and the Physical Region Descriptors exhausted.
Page 244 IDE Configuration 12-12 Intel® 460GX Chipset Software Developer’s Manual...
Page 245: Universal Serial Bus (Usb) Configuration
09-0Bh 0F–1Fh 20–23h 24–3Bh 2C–2Dh 2E–2Fh 30–3Fh 3E–5Fh 61–69h 6A–6Bh 6C–BFh C0–C1h C2-C3h C5-FF Intel® 460GX Chipset Software Developer’s Manual Section 13.3. Mnemonic Register Vendor Identification Device Identification PCICMD PCI Command PCISTS PCI Device Status Revision Identification CLASSC Class Code –...
Page 246: Usb Host Controller Register Descriptions (Pci Function 2)
The VID Register contains the vendor identification number. This register, along with the Device Identification Register, uniquely identifies any PCI device. Writes to this register have no effect. 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. 13.2.2 DID–Device Identification Register (Function 2)
Page 247: Pcists-Pci Device Status Register (Function 2)
Attribute: This 8 bit register contains device stepping information. Writes to this register have no effect. Revision ID Byte. The register is hardwired to the default value. Intel® 460GX Chipset Software Developer’s Manual Universal Serial Bus (USB) Configuration Description 06-07h...
Page 248: Classc-Class Code Register (Function 2)
This register identifies the Serial Bus module as a single Function device. Device Type (DEVICET). 00. Multi-Function device capability for IFB is defined by the HEDT register in Function 0. 13-4 0A-0Bh 0C03h Read only Description Read/Write Description Read only Description Intel® 460GX Chipset Software Developer’s Manual...
Page 249: Usbba-Usb I/O Space Base Address (Function 2)
Default Value: Attribute: Software programs this register with interrupt information concerning the USB. Interrupt Line. The value in this register has no affect on IFB hardware operations. Intel® 460GX Chipset Software Developer’s Manual Universal Serial Bus (USB) Configuration 20-23h 00000001h...
Page 250: Intpn-Interrupt Pin (Function 2)
PCI Address Offset: Default: Attribute: This register provides control and status capability for the legacy keyboard and mouse Functions. 13-6 Read only Description 6A-6Bh 0000h Read/Write Description Read only Description C0-C1h 2000h Read/Write Clear Intel® 460GX Chipset Software Developer’s Manual...
Page 251 60h write. 0 (default) = Disable. Trap/SMI On 60h Read Enable (60REN)–R/W. 1 = Enable I/O Trap and SMI# generation on port 60h read. 0 (default) = Disable. Intel® 460GX Chipset Software Developer’s Manual Universal Serial Bus (USB) Configuration Description...
Page 252: Usbren-Usb Resume Enable
0 to end Global Resume signaling. The 1 to 0 transition causes the port to send a low speed EOP signal. This bit will remain a 1 until the EOP has completed. 13-8 Read/Write Description Base + (00-01h) 0000h Read/Write (WORD write-able only) Description Intel® 460GX Chipset Software Developer’s Manual...
Page 253: Run/Stop, Debug Bit Interaction
PCI Bus errors. Table 13-2. Run/Stop, Debug Bit Interaction SWDBG (Bit 5) Run/Stop (Bit 0) Intel® 460GX Chipset Software Developer’s Manual Universal Serial Bus (USB) Configuration Description If executing a command, the Host Controller completes the command and then stops.
Page 254: Usbsts-Usb Status Register (I/O)
Interrupt On Complete (IOC) Enable. 1= Enabled. 0=Disabled. Resume Interrupt Enable. 1= Enabled. 0=Disabled. Time-out/CRC Interrupt Enable. 1= Enabled. 0=Disabled. 13-10 Base + (02-03h) 0000h Read/Write Clear Description Base + (04-05h) 0000h Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 255: Frnum-Frame Number Register (I/O)
Using this register, the frame length can be adjusted across the full range Intel® 460GX Chipset Software Developer’s Manual Universal Serial Bus (USB) Configuration...
Page 256: Portsc-Port Status And Control Register (I/O)
Host Controller will signal a global resume. Refer to Chapter 11 of the USB Specification for details on hub operation. 15:13 Reserved. Must written as 0s when writing this register. 13-12 Description Base + (10-11h)–Port 0 Base + (12-13h)–Port 1 0080h Read/Write (WORD writeable only) Description Intel® 460GX Chipset Software Developer’s Manual...
Page 257 Current Connect Status–RO. 1=Device is present on port. 0=No device is present. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. Intel® 460GX Chipset Software Developer’s Manual Universal Serial Bus (USB) Configuration Description...
Page 258 Universal Serial Bus (USB) Configuration 13-14 Intel® 460GX Chipset Software Developer’s Manual...
Page 259: Sm Bus Controller Configuration
Offset 00–01h 02–03h 04–05h 06–07h 09-0Bh 0C-1Fh 20-23h 24–3Bh 2C–2Dh 2E–2Fh 30–3Fh 3E-3Fh 41-FFh Intel® 460GX Chipset Software Developer’s Manual Mnemonic Register Vendor Identification Device Identification PCICMD PCI Command PCISTS PCI Device Status Revision Identification CLASSC Class Code – Reserved Base Address Register –...
Page 260: System Management Register Descriptions
The VID Register contains the vendor identification number. This register, along with the Device Identification Register, uniquely identifies any PCI device. Writes to this register have no effect. 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. 14.2.2 DID–Device Identification Register (Function 3)
Page 261: Pcists-Pci Device Status Register (Function 3)
Address Offset: Default Value: Attribute: This 8 bit register contains device stepping information. Writes to this register have no effect. Revision ID Byte. The register is hardwired to the default value. Intel® 460GX Chipset Software Developer’s Manual Description 06-07h 0280h Read/Write Description Initial Stepping = 00h.
Page 262: Classc-Class Code Register (Function 3)
I/O space. 14.2.8 SVID–Subsystem Vendor ID (Function 3) Address: Default Value: Attribute: 15:0 Subsystem Vendor ID. 14-4 09-0Bh 0C0500h Read only Description 20-23h 00000001h Read/Write Description 2C-2Dh 0000h Read only Description Intel® 460GX Chipset Software Developer’s Manual...
Page 263: Sid-Subsystem Id (Function 3)
HST_INT_EN bit needs to be enabled in order for the SMB Host Controller to interrupt or SMI#. Additionally, the SMB Host Controller will not respond to any new requests until all interrupt requests have been. The HST_EN bit does not affect the SMB Slave Port. Intel® 460GX Chipset Software Developer’s Manual 2E-2Fh 0000h...
Page 264: Smbslvc-Smbus Slave Command (Function 3)
14.3 SMBus I/O Space Registers The “Base” address is programmed in the IFB PCI Configuration Space for Function 3, Offset 20h- 23h. 14-6 Read/Write Description Read/Write Description Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 265: Smbhststs-Smbus Host Status Register (I/O)
SMBSHDW1 port. 0 = SMBus interrupt not caused by address match to SMBSHDW1 port. This bit is only set by hardware and can only be reset by writing a 1 to this bit position. Intel® 460GX Chipset Software Developer’s Manual Base + (00h) Read/Write...
Page 266: Smbhstcnt-Smbus Host Control Register (I/O)
SMBus controller host interface to Function normally. Interrupt Enable (INTEREN)–R/W. 1 = Enable the generation of interrupts upon the completion of the current host transaction. 0 = Disable. 14-8 Description Base + (02h) Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 267: Smbhstcmd-Smbus Host Command Register (I/O)
1 and 32 for block command counts. A count of 0 or a count above 32 will result in unpredictable behavior. For block reads, the count received from the SMBus device is stored here. Intel® 460GX Chipset Software Developer’s Manual Base + (03h) Read/Write...
Page 268: Smbhstdat1-Smbus Host Data 1 Register (I/O)
SMBus master generating a transaction with an address that matches the SMBSHDW1 register. 0 = Disable. 14-10 Base + (06h) Read/Write Description Base + (07h) Read/Write Description Base + (08h) Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 269: Smbslvdat-Smbus Slave Data Register (I/O)
SLAVE DATA (SMB_SLV_DATA)–RO. This field contains the data value which was transmitted during an external SMBus master access whose address field matched one of the slave shadow port addresses or the SMBus host controller slave port address of 10h. Intel® 460GX Chipset Software Developer’s Manual Description –...
Page 270 SM Bus Controller Configuration 14-12 Intel® 460GX Chipset Software Developer’s Manual...
Page 271: Pci/Lpc Bridge Description
The IFB provides the functionality of two 82C59 interrupt controllers. The two controllers are cascaded so that 13 external and three internal interrupts are possible. The master interrupt controller provides IRQ [7:0] and the slave interrupt controller provides IRQ [15:8]. The three Intel® 460GX Chipset Software Developer’s Manual 15-1...
Page 272: Programming The Interrupt Controller
CNTRL-2, the slave controller. Within the IFB interrupt unit, IRQ2 on CNTRL-1 is used to cascade the INTR output of CNTRL-2. Consequently, bit-2 of ICW3 on CNTRL-1 is set to a 1, and the other bits are set to 0's. 15-2 Intel® 460GX Chipset Software Developer’s Manual...
Page 273: End Of Interrupt Operation
ICW4 must be programmed on both controllers. At the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in an Intel Architecture-based system. 15.2.1.2...
Page 274: Modes Of Operation
There are two ways to accomplish automatic rotation using OCW2; the Rotation on Non-Specific EOI Command (R=1, SL=0, EOI=1) and the Rotate in Automatic EOI Mode which is set by (R=1, SL=0, EOI=0) and cleared by (R=0, SL=0, EOI=0). 15-4 Intel® 460GX Chipset Software Developer’s Manual...
Page 275: Cascade Mode
Each Interrupt Controller in the cascaded system must follow a separate initialization sequence and can be programmed to work in a different mode. An EOI Command must be issued twice: once for the master and once for the slave. Intel® 460GX Chipset Software Developer’s Manual PCI/LPC Bridge Description 15-5...
Page 276: Edge And Level Triggered Mode
In the Special Mask Mode, when a mask bit is set to 1 in OCW1, it inhibits further interrupts at that level and enables interrupts from all other levels (lower as well as higher) that are not masked. 15-6 Intel® 460GX Chipset Software Developer’s Manual...
Page 277: Reading The Interrupt Controller Status
11 interrupts: 3 - 7, 9-12, 14 or 15. PCLK is used to synchronize the PIRQx# inputs. The PIRQx# lines are run through an internal multiplexer that assigns, or routes, an Intel® 460GX Chipset Software Developer’s Manual PCI/LPC Bridge Description...
Page 278: Serial Interrupts
Once the Start frame has been initiated, all of the serial interrupt peripherals must start counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of 1 clock each: a Sample phase, a Recovery Phase, and a Turn-around phase. 15-8 Intel® 460GX Chipset Software Developer’s Manual...
Page 279: Serirq Frames
If SERIRQ is low for 3 clocks, then the next mode is the Continuous mode. Only the IFB may initiate a Start Frame in the second clock (or more) after the rising edge of the Stop Frame. Intel® 460GX Chipset Software Developer’s Manual PCI/LPC Bridge Description Table 15-1.
Page 280: Timer/Counters
The interval timer is an I/O-mapped device. Several commands are available: The Control Word Command specifies: • Which counter to read or write. • The operating mode. • The count format (binary or BCD). 15-10 Intel® 460GX Chipset Software Developer’s Manual...
Page 281 16-bit or binary-coded decimal (BCD) format. After writing the control word, a new count may be written at any time. The new value will take effect according to the programmed mode. Intel® 460GX Chipset Software Developer’s Manual PCI/LPC Bridge Description 15-11...
Page 282: Read Operations
For example, if the Counter is programmed for two byte counts, the following sequence is valid: 1. Read least significant byte. 2. Write new least significant byte. 3. Read most significant byte. 4. Write new most significant byte. 15-12 Intel® 460GX Chipset Software Developer’s Manual...
Page 283: Real Time Clock
RAM block have very specific Functions. The first ten are for time and date information. The next four (0Ah to 0Dh) are registers, which configure and report RTC Functions. Intel® 460GX Chipset Software Developer’s Manual PCI/LPC Bridge Description 15-13...
Page 284: Rtc Registers And Ram
71h (73h) is written with data or read for data. This scheme is shown in Table 15-2. Table 15-2. RTC (Standard) RAM Bank Index Address 15-14 0Eh - 7Fh Intel® 460GX Chipset Software Developer’s Manual Name Seconds Seconds Alarm Minutes Minutes Alarm Hours...
Page 285 PIE bit is set in register B. Otherwise this tap will set the PF flag of register C. If the periodic interrupt is not to be used, these bits should all be set to zero. Intel® 460GX Chipset Software Developer’s Manual NA - This register is not affected by any system reset signal.
Page 286 Alarm Flag (AF): Alarm Flag will be high after all Alarm values match the current time. Update-ended Flag (UF): Updated-ended flag will be high immediately following an update cycle for each second. Reserved. Read as 0. 15-16 X0000XXXb Read/Write Description Read/Write Description Intel® 460GX Chipset Software Developer’s Manual...
Page 287: Rtc Update Cycle
A write cycle to those locations will have no effect. A read cycle to those locations will not return the actual location value. Once enabled, this Function can only be disabled by a hard reset. Intel® 460GX Chipset Software Developer’s Manual NA - This register is not affected by any system reset signal. Read/Write...
Page 288 PCI/LPC Bridge Description 15-18 Intel® 460GX Chipset Software Developer’s Manual...
Page 289: Ifb Power Management
Table 16-1. IFB Power States and Consumption ACPI State/ Substate S0/C0 S0/C1 Intel® 460GX Chipset Software Developer’s Manual Description ON: CPU operating a full speed with no latencies. Auto Halt: CPU has executed a Halt instruction. Returns to the S0/C0 state based on a break event.
Page 290: Ifb Power Planes
After n minutes of no system activity (where n is determine by the SMM handler), the SMM handler can decide to put the system into a lower power state. Not to be confused with the above periodic SMI timer. Intel® 460GX Chipset Software Developer’s Manual...
Page 291: Sci Generation
Upon exit from any Sleep states, the WAK_STS bit will be set. • Upon exit from any Sleep state, the SLP_TYP bits will contain the originally programmed values. Intel® 460GX Chipset Software Developer’s Manual Table 16-3. Each source can be individually enabled/disabled. Comment Time-out every 2.34 seconds.
Page 292: Acpi Bits Not Implemented By Ifb
Not needed for standard desktop. Stopping CPU clock not supported. GPI not needed for desktop Lid not needed for desktop GPI not needed for desktop Lid not needed for desktop Power state not needed for desktop Intel® 460GX Chipset Software Developer’s Manual Comment...
Page 293: Handling Of Power Failures In Ifb
In this case, the system may have to always boot after a power failure (except if placed into the S5 state due to Power Button Override). Intel® 460GX Chipset Software Developer’s Manual RTC_EN must be set for the wake event...
Page 294 IFB Power Management 16-6 Intel® 460GX Chipset Software Developer’s Manual...

Intel 460GX Software Developer’s Manual

1 Introduction

2 Register Descriptions

3 System Architecture

4 System Address Map

5 Memory Subsystem

6 Data Integrity and Error Handling

7 AGP Subsystem

8 WXB Hot-Plug

9 IFB Register Mapping

10 IFB Usage Considerations

11 LPC/FWH Interface Configuration

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Summary of Contents for Intel 460GX