Traffic Priority; Coherency, Translation And Types Of Agp Traffic - Intel 460GX Software Developer’s Manual

The range may lie above the top of physical memory. Or the range may be placed in one of the gaps
used to map addresses to PCI, and have that gap marked as reserved and not usable for addressing
PCI devices.
In the first case, the virtual range used by the graphics card may be above or below the 4 GB
boundary. If it is above, then it can be placed anywhere in the 40 bit address range supported by the
GXB. This requires dual-address cycles (DAC) on PCI-type accesses or for AGP-type accesses
which use the sideband signals or the DAC command with PIPE#. Having the virtual range above
the top of memory means that s/w can allocate the full GART space per GXB at boot time and not
worry about it again. The address must be translated by the GART to a 36-bit address, since only
36 physical bits are supported after the GART. In this case, there is a special BAR that is used by
the firmware to know how much space to allocate for AGP. This special BAR is the BAPBASE
register in the GXB and is exactly the same as the standard PCI-defined BAR, except that it is not
in the PCI-defined Header space.
In the second case, one can map out the required region by using the standard BAR configuration
register in the SAC. Firmware will read the BAR on the AGP card itself and give it the address
space it needs. It will then read the BAR on the GXB to see how much AGP space is being
mapped. It will then use the PCIS register for Device 14h to allocate this space. The PCIS registers
for Devices 15h, 16h, and 17h will all be set to that of 14h, which in effect disables 15-17h.
The graphics card can issue addresses to the non-AGP space using AGP protocol. The addresses it
puts out are the physical memory addresses, the same as PCI cards or the processor does today.
The physical memory used for graphics may change during run-time. One application may need
only a few megabytes of AGP space and would only get that many bytes of physical space from the
o.s. It would only program the few entries in the GART that it needed. A later application might ask
for hundreds of MBs of physical memory and then map more entries in the GART. When that
application finished it could release the physical memory back to the O.S. In all cases the virtual
addresses used are allocated at boot/config time. They do not change during runtime, only the
mapping of the physical memory they point to changes.
7.2.2

Traffic Priority

The AGP specification has both hi-priority and low-priority AGP transfers as well as PCI transfers.
The GXB will do hi-priority requests ahead of any low-priority or PCI requests. The SAC will not
prioritize any AGP traffic over other system traffic. So, except for the GXB, the chipset has no
concept of traffic priority. Since the chipset's intent is to provide the best service to all agents,
trying to give one agent priority does not fit well. Since memory is highly interleaved, having the
GXB move hi-priority traffic ahead of low-priority traffic should be sufficient to provide the
latency needed by the traffic.
Since the processor and PCI traffic must appear on the system bus, a new address may appear every
3 clocks from any coherent agent. The other 2 clocks are used for moving non-coherent traffic to
the memory controller. Thus the processor can never hold off AGP traffic.
7.2.3

Coherency, Translation and Types of AGP Traffic

Table 7-1
means an address that hits in the translation window. DRAM-space is an address which is a
physical DRAM location. PCI-space is an address that would normally be directed to a PXB and a
PCI device. Both the DRAM-space and the PCI-space lie outside the AGP-space. These areas must
not overlap. The destination of the request is determined by address registers in configuration
space.
Intel® 460GX Chipset Software Developer's Manual
shows the types of traffic versus address range and the resulting behavior. AGP-space
AGP Subsystem
7-7