Intel 460GX Software Developer’s Manual page 46

Register Descriptions
2.4.5.6 NERR_GART
Function Number:
Address Offset:
Default Value:
Sticky:
This register records all error conditions detected in the GART logic after the first error. Errors
recorded in FERR_GART are not recorded here.
Bits
7:0
2.4.5.7 PAC_ERR: PCI Address & Cmd First Error
Function Number:
Address Offset:
Default Value:
Sticky:
These registers record and latch the Address and Command information on the PCI Bus for the first
error detected.
Bits
63:46
45
44
43:40
39:0
2.4.5.8 PD_ERR: PCI Data First Error
Function Number:
Address Offset:
Default Value:
Sticky:
These registers record and latch the Data and Byte Enable information on the PCI Bus for the first
error detected.
Bits
63:37
36
35:32
31:0
2-26
BFN+1
8Eh
00h each
Yes
Description
See FERR_GART for definitions of these bits.
BFN+1
A0h
0000000000h each
Yes
Description
reserved(0)
PCI Parity (2nd phase of DAC, not defined for non-DAC address).
PCI Parity (if DAC, this is the parity of the first half of the address).
PCI Command - Command of Error.
PCI Address - Address Received on Error. (possible DAC address).
BFN+1
A8h
00h each
Yes
Description
reserved(0)
PCI Parity.
PCI Byte Enable [3:0] - Byte Enable of Error.
PCI Data - Data of Error.
Size:
Attribute:
Locked:
Size:
Attribute:
Locked:
Size:
Attribute:
Locked:
Intel® 460GX Chipset Software Developer's Manual
8 bits
Read/Write Clear
No
64 bits
Read/Write
No
64 bits
Read/Write
No