Intel 460GX Software Developer’s Manual page 36

Register Descriptions
5
4
3
2
1
0
2.4.2.14 SDC_NERR: SDC Next Error Status Register
Bus CBN, Device Number: 04h
Address Offset:
Default Value:
This register records the next error status within the SDC. Writing a '1' to this register will clear
the bit in both SDC_NERR and the same bit in SDC_FERR.
Bits
31:0
2.4.2.15 PCMD_FERR: Command on First PCMD Parity Error
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the data associated with the first parity error detected on the
PCMD bus.
Bits
31:19
18
17
16:0
2.4.2.16 PITID_FERR: Data on First PITID Parity Error
Bus CBN, Device Number:
Address Offset:
Default Value:
2-16
System Bus Double Bit Error (DEDF)
ECC Double Bit Error Detected on system bus.
System Bus Single Bit Error (SECF)
ECC Single Bit Error Detected on system bus.
SDC Card A Double Bit Error (DED1)
ECC Double Bit Error Detected from Memory Card A.
SDC Card A Single Bit Error (SEC1)
ECC Single Bit Error Detected from Memory Card A.
SDC Card B Double Bit Error (DED0)
ECC Double Bit Error Detected from Memory Card B.
SDC Card B Single Bit Error (SEC0)
ECC Single Bit Error Detected from Memory Card B.
84-87h
0000h
Description
See SDC_FERR for bit definitions.
04h
88-8Bh
00h
Description
reserved(0)
If set then the error was detected on the 1
Otherwise, these fields contain the information from the 2
transfer.
Parity of Error
PCMD - Private Data Command value of Error.
04h
8Ch
0h
Size:
Attribute:
Size: 32 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
st
half of the double–pumped transfer.
nd
Size: 8 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Intel® 460GX Chipset Software Developer's Manual
32 bits
Read/Write to Clear
half of the double-pumped