Pxb - Intel 460GX Software Developer’s Manual

Chipset system
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Register Descriptions
0
2.4.3.2
CMND_FERR: Command on First Error
Bus CBN, Device Number: 05h,06h
Address Offset:
Default Value:
This register records and latches the data on the SAC-MAC Command Bus for the first error
detected.
Bits
23:22
21:19
18:17
16:0
2.4.4

PXB

2.4.4.1
ERRSTS: Error Status Register
Address Offset:
Default Value:
This register records error conditions detected from the PCI bus (not already covered in PCISTS),
from the Expander Bus, and performance monitoring events.
The register is sticky through reset; that is, the contents of the register remain unchanged during
and following the assertion of X(0,1)RST#. This allows system recovery software invoked
following a forced reset to examine the flags to determine the cause of an error. Once set, the flags
remain set until explicitly cleared by software or a power-good reset.
Bits
7
6
5
4
2-22
Parity Error - CMND
Parity Error Detected on SAC-MAC CMND Bus. Look in CMND_FERR Register to
isolate. When the error is detected, the MAC will complete those operations which have
a RAS pending, and stop. No new RAS cycles will be issued after the parity error and that
card is effectively dead.
9Ch
0000h
Description
reserved (0)
Row address [2:0]
Command [1:0]
MA[16:0]
44h
00h
Description
reserved(0).
PERR# observed on PCI Bus
This flag is set if the PXB detects the PERR# input asserted, and the PXB was not the
asserting agent. This flag may be configured to assert SERR# or PERR# in the ERRCMD
register. This bit remains set until explicitly cleared by software writing a 1 to this bit.
Parity Error on Received PCI Data
This flag is set if the PXB detects a parity error on data being read from the PCI bus. This
flag may be configured to assert SERR# or PERR# in the ERRCMD register. This bit
remains set until explicitly cleared by software writing a 1 to this bit.
Parity Error on PCI Address
This flag is set if the PXB detects a parity error on the PCI address. This flag may be
configured to assert SERR# in the ERRCMD register. This bit remains set until explicitly
cleared by software writing a 1 to this bit.
Function Number: 00h,01h
Size:
Attribute:
Size:
8 bits
Attribute:
Read/Write Clear, Sticky
Intel® 460GX Chipset Software Developer's Manual
24 bits
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