Serial Interrupts; Protocol - Intel 460GX Software Developer’s Manual

PCI/LPC Bridge Description
individual PIRQx# line to any one of 11 IRQ inputs. The assignment is programmable through the
PIRQx Route Control registers. One or more PIRQx# lines can be routed to the same IRQx input.
If interrupt steering is not required, the Route Registers can be programmed to disable steering.
Bits 0-3 in each PIRQx Route Control register are used to route the associated PIRQx# line to an
internal IRQ input. Bit 7 in each register is used to disable routing of the associated PIRQx#.
The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI
Board to share a single line across the connector. When a PIRQx# is routed to specified IRQ line,
the software must change the IRQ's corresponding ELCR bit to level sensitive mode.
15.3

Serial Interrupts

The IFB supports a serial IRQ scheme. Because more than one device may need to share the single
serial IRQ signal, an Open Collector signaling scheme is used. Timing is based on the PCI Clock.
If the PCI clock is inactive when a device needs to signal an interrupt, the CLKRUN# signal must
first be asserted by the device to restart the PCI clock.
The serial IRQ configuration is handled via the PCI configuration space. No other registers are
associated with the scheme.
15.3.1

Protocol

Serial interrupt information is transferred using three types of frames: a Start Frame, one or more
IRQ Data frames, and one Stop frame. There are also two modes of operation: Quiet Mode and
Continuous Mode.
15.3.1.1 Quiet (Active) Mode
To indicate an interrupt, the peripheral brings the SERIRQ signal low for one clock, and then tri-
states it. This brings all the state machines from IDLE to the ACTIVE states.
The IFB will then take control of the SERIRQ signal by driving it low on the next clock, and will
continue driving it low for 3-7 clocks more (programmable). Thus the total number of clocks low
will be 4-8. After those clocks, the IFB will drive SERIRQ high for one clock and then tri-state the
signal.
15.3.1.2 Continuous (Idle) Mode
In this mode, the IFB initiates the START frame, rather than the peripherals. Typically this is done
to update IRQ status (acknowledges). The IFB will drive SERIRQ low for 4, 6, 8 clocks depending
on bits SERIRQC register (Function 0), bits [1:0].
This is the default mode after reset, and can be used to enter the Quiet mode.
15.3.1.3 Data Frame
Once the Start frame has been initiated, all of the serial interrupt peripherals must start counting
frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of
1 clock each: a Sample phase, a Recovery Phase, and a Turn-around phase.
15-8 Intel® 460GX Chipset Software Developer's Manual