Pci/Lpc Bridge Description; Pci Interface; Transaction Termination; Parity Support - Intel 460GX Software Developer’s Manual

PCI/LPC Bridge Description

15.1

PCI Interface

The IFB incorporates a fully PCI Bus compatible master and slave interface. As a PCI master, the
IFB runs cycles on behalf of DMA, Bus Master IDE, and USB. The IFB implements an internal
arbiter to request the PCI bus IDE and USB for these master Functions.
All memory cycles run by the IFB master interface target system DRAM.
As a PCI slave, the IFB responds to memory cycles destined for the firmware and I/O cycles to the
integrated legacy Functions (8237, 8254, 8259), the integrated IDE controller, and the relocate-able
I/O spaces for ACPI, IDE, USB, and SM Bus.
15.1.1

Transaction Termination

The IFB supports the PCI cycle termination as described in the PCI Local Bus specification. IFB
As Master–Master-initiated Termination: The IFB supports three forms of master-initiated
termination: 1.) Normal termination of a completed transaction, 2.) Normal termination of an
incomplete transaction due to time-out (applies to line buffer operations-IDE Bus Master, 3.)
Abnormal termination due to the slave not responding to the transaction (Abort) The IFB As a
Master–Response to Target-initiated Termination: As a master, the IFB responds correctly to
the target-termination– Target-Abort, Retry, or Disconnect.
IFB as a Target–Target-initiated Termination: The IFB supports three forms of Target-initiated
Termination– Disconnect, Retry, and Target Abort.
15.1.2

Parity Support

As a master, the IFB generates address parity for read/write cycles and data parity when the IFB is
providing the data. As a slave, the IFB generates data parity for read cycles. The IFB does not
check parity and does not generate SERR# due to an address parity error. However, the IFB does
generate an NMI when another PCI device asserts SERR# (if enabled).
PAR is the calculated parity signal. PAR is even parity and is calculated on 36 bits–AD[31:0]
signals plus C/BE[3:0]#. PAR is always calculated on 36 bits, regardless of the valid byte enables.
PAR is valid one PCI clock after the corresponding address or data phase.
15.1.3

PCI Arbitration

The IFB arbitrates for the PCI Bus through the PHOLD# and PHLDA# signals.
15.2

Interrupt Controller

The IFB provides the functionality of two 82C59 interrupt controllers. The two controllers are
cascaded so that 13 external and three internal interrupts are possible. The master interrupt
controller provides IRQ [7:0] and the slave interrupt controller provides IRQ [15:8]. The three
Intel® 460GX Chipset Software Developer's Manual
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