Access Restrictions; Partitioning; Device Mapping On Bus Cbn - Intel 460GX Software Developer’s Manual

Register Descriptions
to a PCI bus. Reads result in data being returned by the xXB through the SAC to the system
bus.
•
Otherwise, the access is forwarded to the xXB to be placed on the PCI bus (or AGP bus) as a
Configuration Read or Configuration Write cycle. Reads will result in data being returned
through the xXB and SAC back to the system bus, just as in normal Outbound Read
operations.
2.2

Access Restrictions

The 460GX chipset supports PCI configuration space access using the mechanism denoted as
Configuration Mechanism #1 in the PCI specification.
The 460GX chipset internal registers (both I/O Mapped and Configuration registers) are accessible
by the Host CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit)
quantities, with the exception of CONFIG_ADDRESS which can only be accessed as a Dword. All
multi-byte numeric fields use "little-endian" ordering (i.e. lower addresses contain the least
significant parts of the field).
2.2.1

Partitioning

Each SAC, SDC, MAC, PXB, WXB, GXB, each AGP bus below an GXB, and each PCI bus below
an PXB or WXB, has an independent configuration space. None of the registers are shared between
the spaces; that is, the SAC, and each PCI bus in the PXB, have separate control and status
registers.
Configuration registers are accessed using an "address" comprised of the PCI Bus Number, the
Device Number within the bus, and the Register Number within the Device.
Accesses to devices on Bus #0 and Bus #(CBN) are serviced by the 460GX chipset depending on
their device number. Device 10h on Bus #0 is mapped to the SAC; it contains the programmable
Chipset Bus Number. All other chipset devices reside on bus CBN.
The DEVNPRES register is used to determine which chipset devices are present; see
mapping information.
Table 2-1. Device Mapping on Bus CBN
No.
00h
01h
02h
03h
04h
05h
06h
07h
08h-0Fh
a. This is the compatibility bus (where the boot vector is always directed).
Configuration registers located in the SDC are accessed over the private data bus. The SAC
translates CF8/CFC accesses to SDC registers into configuration commands over the PDB.
Configuration registers located on the memory boards are accessed over the I2C port. The SAC
2-2
Device
SAC 10h
SAC 11h
reserved 12h
reserved 13h
SDC 14h
Memory Card A 15h
Memory Card B 16h
reserved 17h
reserved 18h-1Fh
No. Device
Expander 0, Bus a
Expander 0, Bus b
Expander 1, Bus a
Expander 1, Bus b
Expander 2, Bus a
Expander 2, Bus b
Expander 3, Bus a
Expander 3, Bus b
reserved
Intel® 460GX Chipset Software Developer's Manual
Table 2-1 for
a