Delayed Read Matching Criteria - Intel 460GX Software Developer’s Manual

Table 7-2. Delayed Read Matching Criteria
Command
Any Memory Read
When a DRC is valid in the GXB, a 2
Specification. When the timer expires the DRC is discarded and the associated delayed read
matching registers are cleared. This condition is optionally treated as an error. See the "Error"
Chapter for details.
7.2.7.5 Inbound I/O Reads
I/O reads on the PCI bus are not claimed by the GXB.
7.2.7.6 Inbound Writes
Memory write requests may be directed to the memory only. All write requests are posted. A series
of buffers in both the GXB and SAC allow posted writes to be accumulated and serviced as
convenient. The actual data is forwarded to buffers in the SAC, where it is held until the request
can be snooped on the system bus.
Writes to Memory
The snoops on the system bus for PCI Stream AGP-DRAM writes will be initiated by using the
Memory Read and Invalidate of Length=0 system bus transaction. Any implicit write back due to
snoop hit to a modified line will be snarfed by the SDC. The write back data will be merged with
the AGP write data within the SDC.
Writes to memory use the linear burst ordering provided on the AGP bus.
The Write and Write & Invalidate commands have small differences, as follows:
Write
Write & Invalidate By definition this must be an aligned cache line worth of data. It is forwarded
Note that the actual writing of the data into memory may be delayed. However, in effect, the data
can be counted as being written in the memory, since no other write to that location may pass this
write.
7.2.7.7 Inbound I/O Writes
I/O writes on the PCI bus are not claimed by the GXB.
Intel® 460GX Chipset Software Developer's Manual
Address BEs
Match Match
15
PCI clock timer is started as described in the PCI 2.2
Accumulates posted data until (a) a cache line boundary is reached, or (b) the
master disconnects, before forwarding the request to the SAC. The SAC
therefore deals with a single packet that represents up to a cache line of data.
The SAC places a cache-line snoop on the bus, and the SDC handles the writing/
merging of the partial data into memory. The Expander bus command is a write.
to the SAC as a cache line of data. The SAC places a cache-line snoop on the
bus for each line of data, and the SDC writes the full cache line into memory.
In the event the snoop results in a HITM#, the write back data from the
processor is discarded by the SDC.
AGP Subsystem
7-11