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Intel 440GX Design Manual

Intel 440GX Design Manual

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Intel
440GX AGPset
Design Guide
March 1999
Order Number:
290651-001

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  • Page 1 ® Intel 440GX AGPset Design Guide March 1999 Order Number: 290651-001...
  • Page 2 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

  • Page 3: Table Of Contents

    2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 Pre-Layout Simulation (Sensitivity Analysis)...2-13 Placement & Layout...2-14 Post-Layout Simulation ...2-14 2.5.1 ® Intel 440GX AGPset Design Guide ® ® Pentium II Processor / Intel 440GX AGPset Overview ...1-3 ® ® Intel Pentium II Processor...1-3 ®...
  • Page 4 4 DIMM Routing Guidelines [NO FET]...2-30 PCI Bus Routing Guidelines ...2-30 ® Decoupling Guidelines: Intel 440GX AGPset Platform ...2-31 ® Intel 440GX AGPset Clock Layout Recommendations...2-32 2.9.6.1 Clock Routing Spacing ...2-32 2.9.6.2 System Bus Clock Layout...2-32 2.9.6.3 PCI Clock Layout...2-33 2.9.6.4...
  • Page 5 Slot 1 Test Tools ...4-1 Debug/Simulation Tools...4-1 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 ® Intel 440GX AGPset Design Guide PIIX4E Connections...3-16 IDE Routing Guidelines...3-20 3.7.2.1 Cabling...3-20 3.7.2.2 Motherboard ...3-20 PIIX4E Power And Ground Pins ...3-22 Logic Analyzer Interface (LAI)...4-1 In-Target Probe (ITP)...4-1 Bus Functional Model (BFM) ...4-2...
  • Page 6 5.2.2 5.2.3 Other Processor Components ...5-4 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 ® Intel 440GX AGPset Platform Reference Design ... A-1 ® ® Intel Pentium II Processor LAI Issue ...4-2 Debug Logic Recommendations...4-4 4.3.2.1 Debug Considerations ...4-5 Debug Layout ...4-5 4.3.3.1 Design Considerations ...4-5...
  • Page 7 Current Solution With Existing FET Switches ...3-15 Series Resistor Placement for Primary IDE Connectors...3-21 Dual Footprint Flash Layouts ...3-25 nterfacing Intel’s Flash with PIIX4E in Desktop ...3-26 Interfacing Intel’s Flash with PIIX4E in Desktop ...3-28 PWRGOOD & PWROK Logic ...3-29 LAI Probe Input Circuit...4-3...
  • Page 8 Recommended Trace Lengths for Dual Processor Designs2...2-8 SET Trace Length Requirements ...2-9 Recommended 100 MHz System Flight Time Specs ...2-13 System Timing Requirements for Validating Setup/Hold Windows ...2-16 Ringback Guidelines at the Intel ® Intel System Timing Equations ...2-17 ®...

  • Page 9: Revision History

    Revision History Date Revision Description 3/99 -001 Initial Release. ® Intel 440GX AGPset Design Guide...

  • Page 10: Intel ® 440Gx Agpset Design

    ® Intel 440GX AGPset Design Guide...

  • Page 11: Introduction

    Introduction...

  • Page 13: About This Design Guide

    Chapter 1 also provides a general component overview of the Intel Intel 440GX AGPset. The Wired for Management Initiative is also discussed which is an Intel initiative to improve the manageability of desktop, mobile, and server systems. This chapter also provides design recommendations which Intel feels will provide flexibility to cover a broader range of products within a market segment.

  • Page 14: References

    ® • Intel 440GX AGPset Datasheet (WWW; order number 290638) • Intel 82371EB PCI-to-ISA/IDE Xcelerator (PIIX4) Datasheet (WWW; order number 290562) • Intel Architecture Software Developer’s Manual, Volume 1; Basic Architecture (order number 243190) • Intel Architecture Software Developer’s Manual, Volume 2; Instruction Set Reference (order number 243191) •...

  • Page 15: Intel ® Pentium ® Ii Processor

    New applications and hardware add-ins from third party vendors are being developed that take advantage of the MMX™ technology incorporated into the Intel contact your local Intel field sales representative for information on IHVs and ISVs utilizing Intel’s MMX™ technology.
  • Page 16 ® • The Intel 440GX AGPset is the fourth generation chipset based on the Intel processor architecture. It has been designed to interface with the Intel processor’s system bus at 100 MHz. Along with its Host-to-PCI bridge interface, the 82443GX host bridge controller has been optimized with a 100 MHz SDRAM memory controller and data path.

  • Page 17: System Bus Interface

    Figure 1-1 shows a block diagram of a typical platform based on the Intel 82443GX system bus interface supports up to two Intel bus frequency of 100 MHz. The physical interface design is based on the GTL+ specification and is compatible with the Intel DRAM interface (64-bit Data plus ECC).

  • Page 18: Pci Interface

    For more information on the PIIX4E, please refer to thePIIX4 datasheet. 1.3.4 Wired for Management Initiative Wired for Management (WfM) is an Intel initiative to improve the manageability of desktop, and server systems. The goal of WfM is to reduce the Total Cost of Ownership (TCO) through improved manageability in the following four technology areas: •...

  • Page 19: Instrumentation

    Version 2.00 Management Interface (MI) and Component Interface (CI) application programming interfaces and host a DMI v2.00 Service Provider, as defined by the DMTF. Intel's DMI 2.0 Service Provider Software Development Kit (SDK) provides a DMI Service Provider and binaries that support DMI Version 2.00.

  • Page 20: Remote Wake-Up

    See the WOL Header Recommendations document at: ftp://download.intel.com/ial/wfm/wol_v14.pdf. The system BIOS must enable the wake event and provide wake up status. The details of the BIOS requirements can be obtained from the Intel Corporation web site: http://developer.intel.com/ial/WfM/design/rwudt/index.htm 1.3.3.4 Power Management WfM Baseline compliant systems have four distinct power states: Working, Sleeping, Soft Off, and Mechanical Off.

  • Page 21: General Design Recommendations

    MAA14 and MAB14 are the same as MAA-13 and MAB-13 on the 82443BX. ® 2. Intel 440GX AGPset supports 100 MHz system bus and 100 MHz SDRAM Memory only. 3. There is no 3 DIMM support with the Intel 440GX AGPset. ®...
  • Page 22 Introduction ® Intel 440GX AGPset Design Guide 1-10...

  • Page 23: Motherboard Design

    Motherboard Design...

  • Page 25: Motherboard Layout And Routing Guidelines

    BGA Quadrant Assignment Intel assigned pins on the 82443GX to simplify routing and keep board fabrication costs down, by permitting a motherboard to be routed in 4-layers. 82443GX. The component placement on the motherboard should be done with this general flow in mind.

  • Page 26: Example Atx Placement For A Up Pentium

    ATX and NLX form factor designs. ATX Form Factor: 1. The ATX placement and layout below is recommended for single (UP) Intel processor / Intel 2. The example placement below shows 4 PCI slots, 2 ISA slots, 4 DIMM sockets, and one AGP connector.

  • Page 27: Board Description

    NLX Form Factor: 1. The NLX placement and layout below is recommended for a single (UP) Intel processor / Intel 2. The example placement below shows one Slot 1 connector, 4 DIMM sockets, and an AGP compliant device down. 3. For an NLX form factor design, the AGP compliant graphics device may readily be integrated on the motherboard (device down option).

  • Page 28: Four Layer Board Stack-Up

    3 signal plane layers and 3 power plane layers. The second option makes it easier to accommodate all of the power planes required in a Intel If a 6 layer stack-up is used, then it is recommended to route most of the GTL+ bus signals on the inner layers.

  • Page 29: Routing Guidelines

    GTL+ signals. Even when the guidelines are followed, it is still a good idea to simulate as many signals as possible for proper signal integrity, flight time and cross talk. ® Intel 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines Primary Signal Layer (1/2 oz. cu.) 5 mils PREPREG Ground Plane (1 oz.

  • Page 30: Gtl+ Description

    2.3.2 GTL+ Layout Recommendations This section contains the layout recommendations for the GTL+ signals. The layout recommendations are derived from pre-layout simulations that Intel has run using the methodology described in Section 2.3.7, “Design Methodology” on page simulations are included in this section.

  • Page 31: Single Processor Recommended Trace Lengths

    ® 1. Refer to the Intel #42: workaround L1=4.5”. Intel strongly recommends running analog simulations using the available I/O buffer models together with layout information extracted from your specific design. Simulation will confirm that the design adheres to the guidelines.

  • Page 32: Recommended Trace Lengths For Dual Processor Designs2

    1. L4 & L5 are interchangeable 2. It is possible to find working solutions outside the recommendations of show. Intel strongly recommends that any traces that fall outside the recommended lengths be simulated to ensure they meeting timing and signal quality specs.

  • Page 33: Set Trace Length Requirements

    Figure 2-10. Topology for Single Processor Designs With Single-End Termination (SET) 2.3.5.2 SET Trace Length Requirements Intel has performed sensitivity analysis on the SET topology. The required trace lengths for operation at 100 MHz with the SET topology are based on the sensitivity analysis results, and are listed in Table 2-3.

  • Page 34: Additional Guidelines

    Lossless simulations can overstate the amount of ringing on GTL+ signals. Lossy simulations may help to make your results less pessimistic if ringing is a problem. Intel has found the resistivity of copper in printed circuit board signal layers higher than the value of 0.662 -mil...

  • Page 35: Design Methodology

    Intel recommends using the following design methodology when designing systems based on one ® or two Intel Pentium from Intel’s experience developing and validating high speed GTL+ bus designs for the Intel ® Pentium Pro and Intel The methodology provides a step-by-step process which is summarized in process begins with an initial timing analysis and topology definition.

  • Page 36: Performance Requirements

    Setup and hold requirements determine the flight time bounds for the host bus. The system contains multiple paths which must be considered: ® • Intel Pentium • AGPset component driving a Intel ® • Intel Pentium (dual processor systems only) 2-12...

  • Page 37: Topology Definition

    Intel buffer models, core package parasitics, and substrate trace length, impedance and velocity. Intel 440GX AGPset models include the I/O buffers and package traces. Termination resistors should be controlled to within ± 5%. 2.3.11 Simulation Methodology Pre-layout simulation allows the system “solution space”...

  • Page 38: Placement & Layout

    Following layout, extract the traces and run simulations to verify that the layout meets timing and noise requirements. A small amount of trace “tuning” may be required, but experience at Intel has shown that sensitivity analysis dramatically reduces the amount of tuning required.

  • Page 39: Crosstalk And The Multi-Bit Adjustment Factor

    2.6.1 Flight Time Measurement T he timings for the Intel systems, the processor edges fingers are not readily accessible. In most cases, measurements must be taken at the system board solder connection to the Slot 1 connector. To effectively correlate delay measurements to values at the Pentium II processor edge fingers, the Slot 1 connector delay must be incorporated.

  • Page 40: Signal Quality Measurement

    2.6.2 Signal Quality Measurement Signal integrity is specified at the processor core, which is not accessible. Intel has found that there can be substantial miscorrelation between ringback at the edge finger versus the core. The miscorrelation creates instances where a signal fails to satisfy ringback requirements at the edge finger, but passes the ringback specification at the core.

  • Page 41: Timing Analysis

    Pentium II processor substrate. ® Intel 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines ® II Processor and Inte l 440GX AGPset System Timing Equations flight ,min hold ,min flight ,max cycle ,max ®...

  • Page 42: Intel ® Pentium ® Ii Processor And Inte ® L 440Gx Agpset

    Recommended values for system timings are contained in clock generator device come from the CK97 clock driver specification. The PCB skew spec is based on the results of extensive simulations at Intel. The T with systems that use the Intel Table 2-10.

  • Page 43: Agp Layout And Routing Guidelines

    ® Intel 440GX AGPset platform recommendations for the AGP interface. In this document the term “data” refers to AD[31:0], C/BE[3:0]# and SAB[7:0]. The term “strobe” refers to AD_STB[1:0] and SB_STB. When the term data is used, it is referring to one of three groups of data as seen in strobes as it relates to the data in its associated group.

  • Page 44: On-Board Agp Compliant Device ("Down" Option) Layout Guidelines

    3-10). Pull-up resistors should be discrete resistors, as resistor packs Line Length Matching -0.5 in, strobe longest trace -0.5 in, strobe longest trace Line Length Pull-up Stub Length < 0.5 in (Strobes < 0.1in) < 0.5 in (Strobes < 0.1in) Section 3.5.1, ® Intel 440GX AGPset Design Guide...

  • Page 45: On-Board Agp Compliant Device Layout Guidelines

    Table 2-16. Control Signal Line Length Recommendations Width:Space 1:2 (1:4 to Strobe) ® Intel 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines Always 1:2 Strobe Routing 1.0” - 4.5” 1:1 (Data) Routing 1” - 12” 1:2 (Data) Routing Trace...

  • Page 46: 82443Gx Memory Subsystem Layout And Routing Guidelines

    Note: Under certain layouts, crosstalk and ground bounce can be observed on the AD_STB signals of the AGP interface. Although Intel has not observed system failures due to this issue, we have improved noise margin by enhancing the AGP buffers on the 82443GX. For new designs, additional margin can be obtained by following these AGP layout guidelines.

  • Page 47: Matching The Reference Planes

    This low inductance path is provided by decoupling capacitors between Vcc and ground. These decoupling capacitors should be placed as close as possible to the signal vias. ® Intel 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines Register Clock...

  • Page 48: Trace Width Vs. Trace Spacing

    Layout Guidelines: All signals require careful routing for both min and max trace lengths 2-24 CS_A[7:6]#,CS_B[7:6]# CS_A[5:4]#,CS_B[5:4]# CS_A[3:2]#,CS_B[3:2]# CS_A[1:0]#,CS_B[1:0]# SRAS_A# SRAS_B# SCAS_A# SCAS_B# DQM_A[1,5] DQM_A[7,6,4:2,0] DQM_B[1,5] WE_A# WE_B# MAA[14:0] MD[63:0] ~ 16212 FENA MECC[7:0] ~ 16212 DIMM_CLK[3:0] DIMM_CLK[7:4] DIMM_CLK[11:8] DIMM_CLK[15:12] SMB_CLK SMB_DATA Group 0 Group 1 ® Intel 440GX AGPset Design Guide...

  • Page 49: Motherboard Model-Data (Mdxx), 4 Dimms

    Table 2-18. FET Switch DQ Route Example 82443GX Figure 2-20. Motherboard Model—Data (MDxx), 4 DIMMs 82443GX ® Intel 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines 0.3” - 1.0” 0.6” 0.7” - 2.4 ” 0.7” - 2.4” Switch 16212 0.3”...

  • Page 50: Motherboard Model-Dqma[0,2:4,6:7], 4 Dimms

    Figure 2-22. Motherboard Model—DQM_A[1,5], 4 DIMMs Figure 2-23. Motherboard Model—DQM_A[1,5], 4 DIMMs 2-26 1.0” - 3.25” 0.4” - 0.6” 0.4” - 0.6” 1.0” - 3.25” 82443GX 1.0” - 3.25” 82443GX 0.4” - 0.6” 0.4” - 0.6” 0.4” - 0.6” ® Intel 440GX AGPset Design Guide...

  • Page 51: Motherboard Model—Cs_A#/Cs_B#, 4 Dimms

    Figure 2-24. Motherboard Model—DQM_B[1,5], 4 DIMMs Figure 2-25. Motherboard Model—CS_A#/CS_B#, 4 DIMMs Figure 2-26. Motherboard Model—SRAS_A#, 4 DIMMs ® Intel 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines 1.0” - 3.25” 82443GX 1.0” - 4.0” 82443GX 1.0” - 3.0”...

  • Page 52: Motherboard Model: Sras_B#, 4 Dimms

    Table 2-20. Motherboard Model: SCAS_A#, 4 DIMMs Table 2-21. Motherboard Model: SCAS_B#, 4 DIMMs 2-28 1.0” - 3.0” 82443GX 1.0” - 3.0” 82443GX 1.0” - 3.0” 82443GX 0.4” - 0.6” 0.4” - 0.6” 0.4” - 0.6” ® Intel 440GX AGPset Design Guide...

  • Page 53: Motherboard Model: We_A#, 4 Dimms

    Table 2-22. Motherboard Model: WE_A#, 4 DIMMs Table 2-23. Motherboard Model: WE_B#, 4 DIMMs Table 2-24. Motherboard Model: MA_A[14:0], 4 DIMMs ® Intel 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines 1.0” - 3.0” 82443GX 1.0” - 3.0” 82443GX 1.0”...

  • Page 54: Dimm Routing Guidelines [No Fet]

    PCI bus. For more information on the PCI Bus interface, refer to the Intel ® An Intel 440GX AGPset PCI Bus design is basically the same as the Intel ® Intel 440GX AGPset supports 5 PCI Bus masters (excluding the Intel PIIX4E), by the support of 5 PREQ# and PGNT# lines.

  • Page 55: Pci Bus Layout Example

    Figure 2-29. 82443GX Decoupling Note: There are other discrete components for V routing around the 82443GX. ® Intel 440GX AGPset Design Guide Motherboard Layout and Routing Guidelines Figure 2-28. This insures proper “termination” of the PCI Bus ® 440GX AGPset Platform 0.1uF...

  • Page 56: Clock Routing Spacing

    Layout guidelines: Match trace lengths to the longest trace. Clock chip - Processor Clock chip - 82443GX Clock chip - ITP 2-32 ® II processor / Intel 440GX AGPset platform requires a clock synthesizer for 0.014” Trace length 1.0” H + 3.25” 1.0” H + 4.00”...

  • Page 57: Pci Clock Layout

    A 22 Ohm series resistor located at the driver, and a 47 Ohm series resistor located at the receiver. Layout guidelines: 440GX - CKBF (DLKO) CKBF - DIMM (SDRAM Clocks) CKBF - 82443GX (DCLKWR) Note: A single clock output from CKBF is used to drive DCLKWR at the 82443GX. The single clock net should be “T”d as close as possible to the 82443GX.

  • Page 58: Agp Clock Layout

    82443GX will both be the same length. 2-34 22ohm GCLKOUT 22ohm GCLKIN Trace Length A + 3.3” AGPCLK Card Trace Length 0.5” 12” ~3.3” 0.5” 15.3” ® Intel 440GX AGPset Design Guide...

  • Page 59: Design Checklist

    Design Checklist...

  • Page 61: Pull-Up And Pull-Down Resistor Values

    Design Checklist Overview The following checklist is intended to be used for schematic reviews of Intel desktop designs. It does not represent the only way to design the system, but provides recommendations based on the Intel Pull-up and Pull-down Resistor Values Pull-up and pull-down values are system dependent.

  • Page 62: Ii Processor

    BREQ[1:0]# each CPU to BREQ1# of the other. Connect one of these to 82443GX. D[63:0]# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. ® Intel 440GX AGPset Design Guide Leakage ® II Processor Checklist ® II Processor Pin Connection...
  • Page 63 DP: Connect CPUs and PIIX4E, 430 ohm pull-up. UP: 1K ohm pull-up to 2.5V. 47 ohm series resistor to ITP. DP: Separate series resistors then hooked together to ITP. 1K ohm pull-up to 2.5V. ® Intel 440GX AGPset Design Guide Design Checklist Pin Connection...

  • Page 64: Gnd & Power Pin Definition

    8.2K ohm pull-up to 5V is the default for VRM use. Optional override could be used. Also VID[4:0] connect to optional LM79. Table 3-2. GND & Power Pin Definition A102 A106 A110 A114 A118 ® Intel 440GX AGPset Design Guide Pin Connection Vtt (1.5V) VCC3 (3.3V) CORE B105 Design Checklist Reserved (NC) Vcc (5V) B113 B109...

  • Page 65: Processor Signals

    PICCLK must be driven by a clock even if an I/O APIC is not being used. This clock can be as high as 33.3 MHz in a UP system. A DP system utilizing Intel’s I/O APIC (82093AA) has a maximum PICCLK frequency of 16.666 MHz.
  • Page 66 TRST# will accomplish the reset of the port. • If two Vtt regulators are used, one at each end of the bus, Intel recommends connecting the two regulator outputs together with a wide trace that runs the along the same basic path as the GTL+ signals (beware of crosstalk).

  • Page 67: Uni-Processor (Up) Slot 1 Checklist

    • FRCERR# may be left as a no connect for a DP design if FRC mode is not supported. On board termination resistors are not required since they are provided on the Intel processors. • Each processor site should have an isolated Vcc for availability of VRMs with current sharing capabilities if desired.

  • Page 68: Intel ® 440Gx Agpset Clocks

    3.4.1 CK100 - 100 MHz Clock Synthesizer • The system clock which provides 100 MHz to the processor and the Intel and the clocks for the APIC must be +2.5V. • If implemented in the clock chip, pin 28, when strapped low, provides a spread spectrum modulation effect which may help reduce EMI.

  • Page 69: Ckbf - Sdram 1 To 18 Clock Buffer

    20pF capacitor recommended may be required. ® Intel 440GX AGPset Design Guide on the OE pin is needed to enable the buffer. G N D C K B F...

  • Page 70: 82443Gx Host Bridge

    FRAME# GAD[31:0], GC/ BE[3:0]# GCLKIN GCLKOUT ® Intel 440GX AGPset Design Guide CONNECTION Connected to PCI bus. Connected to CPUs. Connected to be 0.4 of VCC . Can be performed by a voltage divider. Connected to CPUs. Connected to CPUs.
  • Page 71 ST[2:0] STOP# SUSTAT# TESTIN# ® Intel 440GX AGPset Design Guide CONNECTION 8.2K ohm pull-ups to 3.3V. Connected to AGP connector. 100K ohm pull-down required. Connect to AGP connector. GTL buffer voltage reference input (1.0V = 2/3 vtt) Connected to CPUs.

  • Page 72: 82443Gx Gtl+ Bus Interface

    ® • The Intel 440GX AGPset does not support the entire Intel bus. For a UP design, on board termination resistors are recommended for the following signals: HD[63:0]#, A[31:3]#, HREQ[4:0]#, RS[2:0]#, HTRDY#, BREQ[0]#, BNR#, BPRI#, DBSY#, DEFER#, DRDY#, ADS#, HIT#, HITM#, HLOCK#, CPURST#. The second set of terminations are provided on the Intel ®...

  • Page 73: 82443Gx Agp Interface

    The AGP signals are PIPE#, SBA[7:0], RBF#, ST[2:0], GADSTBA, GADSTBB, SBSTB, GFRAME#, GIRDY#, GTRDY#, GSTOP#, GDEVSEL#, GREQ#, GGNT#, GAD[31:0], FC/BE[3:0]#, GPAR. 4. When AGP is disabled, tie AGP_Vref to ground. ® Intel 440GX AGPset Design Guide Description Register PMCR[1] AGP Enabled (Default)

  • Page 74: Intel ® 440Gx Agpset Memory Interface

    ® Intel 440GX AGPset Memory Interface 3.6.1 SDRAM Connections Table 3-6. SDRAM Connectivity 82443GX Pins/Connection CKBF buffer outputs DCLK[x:y] CS_A[7:0]# CS_B[7:0]# MAx[9:0]#, MAx10 MAx11# Max12# MAA13#, MAB13 MAA14, MAB14 MDx[63:0] (from FET) MD[63:0] (NO FET) MECC[7:0] Strap for SMBus individual...

  • Page 75: Dimm Solution With Fet Switches

    The clock signal is routed via a PLL to all the SDRAM devices. • Access to registered DIMMs requires an additional clock of leadoff latency, programmable in the 82443GX. ® Intel 440GX AGPset Design Guide DQ 0-71 F E T R 7 1 FENA Design Checklist...

  • Page 76: 82371Eb (Piix4E)

    IGNNE# INIT# INTR ® Intel 440GX AGPset Design Guide Connection Connect to CK100 through a 22 ohm series resistor. Connected to SIO. 8.2K ohm pull-up to VCC3. Part of CPU/bus frequency circuit. 2.7K ohm pull-up to VCC3. Connect to PCI slots and 82443GX.
  • Page 77 PDREQ PGCS#0 PGCS#1 ® Intel 440GX AGPset Design Guide Connection Connected to ISA slots. 4.7K ohm pull-up to VCC. Connected to ISA slots and Ultra I/O. 1K ohm pull-up to VCC. Connected to ISA slots. 1K ohm pull-up to VCC.
  • Page 78 SLP# SMBALERT# / GPI11 ® Intel 440GX AGPset Design Guide Connection Connected to 82443GX. 8.2K ohm pull-up to VCC3. Connected to 82443GX. 8.2K ohm pull-up to VCC3. Connected to IDE through 47 ohm series resistor. 1K ohm pull-up to VCC on the PIIX4E side of the series resistor.
  • Page 79 ZEROWS# ZZ / GPO19 ® Intel 440GX AGPset Design Guide Connection Connect to all devices on SMBus. 2.7K ohm pull-up to VCC3. This value may need to be adjusted based on bus loading. Connected to ISA slots. 1K ohm pull-up to VCC.

  • Page 80: Ide Routing Guidelines

    Table 3-8. IDE Series Termination Signal PDD[15:0] PDA[2:0] PDIOR# PDIOW# PDDREQ PDCS1# PDCS3# PDDACK# IRQ14 RESET# ® Intel 440GX AGPset Design Guide Resistor Signal 33 ohm SDD[15:0] 33 ohm SDA[2:0] 33 ohm SDIOR# 33 ohm SDIOW# 33 ohm SDDREQ 33 ohm...

  • Page 81: Series Resistor Placement For Primary Ide Connectors

    1 inch of the PIIX4E. The series termination resistors are required in either design. ® Intel 440GX AGPset Design Guide 7 4 H C T 1 4 1 0 K o h m P D D 7 5 .

  • Page 82: Piix4E Power And Ground Pins

    Second, an external capacitor of approximately 47pF will help reduce the glitch. ® Intel 440GX AGPset Design Guide circuitry can be shared between 82443GX and the PIIX4E. If pin of the 82443GX. circuit for a minimum voltage drop from VCC...

  • Page 83: Isa Signals

    The LM79 is connected to the X-Bus due to the functionality of the PGCS[1:0]# pins on the PIIX4E. ® Intel 440GX AGPset Design Guide CONNECTION (5V PCI environment) 2.7K ohm pull-up resistors to 5V. (3V PCI environment) 10K ohm pull-up resistors to 3.3V.

  • Page 84: Usb Interface

    USB Interface • Contact your local Intel Field Sales representative for the following Application Note: 82371AB PIIX4 Application Note #1: USB Design Guide And Checklist Rev 1.1. This document discusses details of the PIIX4/PIIX4E implementation of the Universal Serial Bus.

  • Page 85: Flash Design

    OEMs should design motherboards to be flexible. Design in a dual-footprint on the motherboard that accepts both Intel’s 1 Mbit flash chips and 2 Mbit boot block chips. This will make the 1M-to- 2M transition easier by removing the need for PCB changes to accommodate higher density components.

  • Page 86: Nterfacing Intel's Flash With Piix4E In Desktop

    If adding a switch on VPP for write protection, switch to GND instead of VCC. • Connect the DU pin of the 2Mbit devices to GND if anticipating to use the Intel SmartVoltage boot block flash memory family in the future.

  • Page 87: Flash Vpp Recommendations

    Add information on how BIOSCS# elevates the need for control logic and GPO[x] control on • Add information on ISA load consideration and the reduction of the X-bus drivers/control Figure 3-7 illustrates the recommended layout for Intel’s flash devices in desktop designs: ® Intel 440GX AGPset Design Guide...

  • Page 88: System And Test Signals

    Figure 3-7. Interfacing Intel’s Flash with PIIX4E in Desktop SD[7:0] PIIX4E PIIX4 S U S A # GPO[x] SA[17:0] M E M W # M E M R # B I O S C S # 3.14 System and Test Signals •...

  • Page 89: Pwrgood & Pwrok Logic

    The following should be considered when implementing a RESET BUTTON for desktop based systems: ® Intel 440GX AGPset Design Guide Simplified P W R G O O D a n d P W R O K generation logic V C C 3 P W R G O O D t o C P U 4.7K...

  • Page 90: Power Button Implementation

    Do not override this with additional hardware. • If SCI is not enabled: • Enable the power button to generate an SMI and go directly to soft-off or a supported sleep state. ® Intel 440GX AGPset Design Guide Design Checklist 3-30...

  • Page 91: Miscellaneous

    Recommendations for New Board Designs to minimize ESD events that may cause loss of CMOS contents: — Provide a 1uF X5R dielectric, monolithic, ceramic capacitor between the VCCRTC pin of the PIIX4/PIIX4E and the ground plane. This capacitor’s positive connection should not ® Intel 440GX AGPset Design Guide Design Checklist 3-31...

  • Page 92: 82093Aa (Ioapic)

    2.5V. The maximum frequency is 16.666 MHz while the minimum is 14.3 MHz. • APICACK2# (pin 8) - This pin is connected to the Intel • CLK is compatible with 2.5V, 3.3V or 5V input levels. It is typically connected to the APIC clocks that are 2.5V.

  • Page 93: Manageability Devices

    IO address 05h followed by a read of IO address 06h. • VID[4:0]: These inputs allow storage of the voltage identification pin bits for Intel II processors to allow the BIOS to record voltage specification variations.

  • Page 94: 82558B Lom Checklist

    LM79 is tied to the X-Bus. See PIIX4 Datasheet for more details. 3.18.3 82558B LOM Checklist • Refer to Application Note # 383, Intel 82558 LAN on Motherboard Design Guide, for recommended PHY conformance testing (i.e., IEEE testing) and additional LOM design details. •...

  • Page 95: Wake On Lan (Wol) Header

    It is recommended that the BIOS implement the minimum update API interface to allow the BIOS Update stored in BIOS to be updated. Of the two Intel-defined update APIs, it is recommended that the full real mode INT15h interface be implemented. An API calling utility and test tool is available for this interface.

  • Page 96: Design Considerations

    • Verify that all major components, including the 82443GX can be cooled the way they are placed. Contact your local Intel Field Sales representative for the following Application Note: FW82443BX/FW82443GX PCI/AGP Controller Application Note #2: Thermal Design Considerations. This thermal application note contains thermal specifications, thermal solutions and the thermal test methodology for the 82443GX component.

  • Page 97: Design Considerations

    Slot 1 processor in the system during shock and vibration situations. If these Intel enabled retention solutions are used, the motherboard keep out zones and mounting hole requirements must be met. See the ®...

  • Page 98: Layout Checklist

    • Contact your local Intel field sales representative for information on IHVs and ISVs utilizing Intel’s MMX™ technology. • Contact your local Intel Field Sales representative for information on utilizing Intel’s latest AGP technology.

  • Page 99: Debug Recommendations

    Debug Recommendations...

  • Page 101: Slot 1 Test Tools

    While the methodologies suggested are those which Intel believes are most likely to be successful, they are not a substitute for correct design practices nor are they a substitute for other Intel references.

  • Page 102: Bus Functional Model (Bfm)

    • 82443GX IBIS Models • PIIX4E PCI ISA IDE Xcelerator IBIS Models Contact your local Intel Field Sales representative for a copy of these models and to complete the appropriate non-disclosure agreements. 4.2.5 FLO THERM * Model A FLOTHERM* Model is available for the Intel...

  • Page 103: Lai Probe Input Circuit

    Outputs from the Slot 1 connector: • • THERMTRIP# • FERR# ® Intel 440GX AGPset Design Guide 150 - 330 ohm 150 - 330 ohm 1 Kohm 470 - 680 ohm (A pull-down is recommended but a pull-up may be used) 430 ohm 430 ohm...

  • Page 104: Debug Logic Recommendations

    • FLUSH# 4.3.2 Debug Logic Recommendations Debug Recommendations are intended to assist in the development of the Intel processor system and products utilizing it. The following are strongly recommended for early prototype designs only. • Provide a push button reset circuit, do not rely on power-on reset from the power supply. A push-button reset usually results in more repeatable results when debugging initialization problems.

  • Page 105: Debug Considerations

    • Intel recommends using industry standard Voltage Regulator Modules designed for the processor. However, previous VRM modules may not support future processors for Slot 1 unless built to VRM 8.2 specifications..
  • Page 106 After BNR# stops toggling, the PICD[1:0]# signals begin the MP initialization to determine the bootstrap processor. In a single processor boot, two 21-cycle short messages are transmitted on the APIC. (Refer to the Intel III). The following fields are expected and all others are “don’t care.” Note that PICD[1:0]# are active low so the pin electrical levels will be the complement of the numbers presented here.

  • Page 107: Third Party Vendors

    Third Party Vendors...

  • Page 109: Third-Party Vendor Information

    This chapter includes information regarding various third-party vendors who provide products to support the Intel can be used as a starting point for the designer. Intel does not endorse any one vendor, nor guarantee the availability or functionality of outside components. Contact the manufacturer for specific information regarding performance, availability, pricing, and compatibility.

  • Page 110: Voltage Regulator Modules

    Astec Switch Power 5.1.2 Voltage Regulator Control Silicon The following vendors are developing DC-DC converter silicon and reference designs for Intel ® Pentium II processor voltage and current requirements. Generally, VRM 8.1 (5-bit VID) control silicon supports VRM 8.2 requirements.

  • Page 111: Intel ® 440Gx Agpset

    Intel has supplied specifications to clock driver vendors, including the following. The specifications define requirements for Intel 440GX AGPset. Intel tests some clock devices to verify the ability of the industry to meet the Intel specification; there is no formal component qualification.

  • Page 112: Other Processor Components

    Slot 1 retention mechanism, dual retention mechanism, retention mechanism attach mount, and heat sink supports. 5.3.3 Heat sinks Public information; see Intel dimensions are public; an MP-CITR is required to discuss Intel levels. 5.3.4 Heat sink attachment: Rivscrews* and associated tools Public information; see Intel http://developer.intel.com/design/PentiumII/components/index.htm...
  • Page 113 Reference Design Schematics...

  • Page 115: Intel 440Gx Agpset Platform Reference Design

    Several vendors offer components that can be used in this design. This page also shows the In Target Probe (ITP) Connector. The ITP connector is recommended in order to use the In Target Probe tool available from Intel and other tool vendors for Intel ®...
  • Page 116 ® Intel 440GX AGPset Platform Reference Design 82443GX Component (System bus and DRAM Interfaces) This page shows the 82443GX component, System bus and DRAM Interfaces. The 82443GX connects to the lower 32 bits of the CPU address bus and the CPU control signals, and generates DRAM control signals for the memory interface.
  • Page 117 Note: that two LT1587-1.5s (@ 3A) are recommended. ® Intel 440GX AGPset Design Guide ® Intel 440GX AGPset Platform Reference Design generation circuit must be able to provide about 5.0 amps of 22-23 28-30 ), the...
  • Page 118 6-pin optional ATX connector, and the Wake-On-LAN header. Note: a CPU Fan Header is required for the Intel Boxed processor. The dual-color LED circuit is also used to reduce the voltage going to the power supply fan, thus decreasing its speed and quieting the system.

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