Serirq Frames - Intel 460GX Software Developer’s Manual

During the Sample phase, the device drives SERIRQ low if the corresponding interrupt signal is
low. If the corresponding interrupt is high, then the devices will tri-state the SERIRQ signal. It will
remain high due to pull-up resistors.
During the other two phases (turnaround and recovery), no device should drive the SERIRQ signal.
The IRQ/DATA frames have a specific order and usage, as shown in
If an SMI# is activated on frame 3, the IFB will drive its SMI# signal low. This will then generate
an SMI# to the microprocessor if enabled.
Table 15-1. SERIRQ Frames
Data Frame Number
15.3.1.4 Stop Frame
After all of the data frames, a Stop Frame will be done by the IFB. The IFB will drive SERIRQ low
for 2-3 PCI clocks. The number of clocks determines the next mode:
•
If SERIRQ is low for 2 clocks, then the next mode is the Quite Mode. Any device may initiate
a Start Frame in the second clock (or more) after the rising edge of the Stop Frame.
•
If SERIRQ is low for 3 clocks, then the next mode is the Continuous mode. Only the IFB may
initiate a Start Frame in the second clock (or more) after the rising edge of the Stop Frame.
Intel® 460GX Chipset Software Developer's Manual
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PCI/LPC Bridge Description
Table
Usage
UNASSIGNED
IRQ1
SMI#
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
UNASSIGNED
IRQ9
IRQ10
IRQ11
IRQ12
UNASSIGNED
IRQ14
IRQ15
IOCHCK#
PCI INTA#
PCI INTB#
PCI INTC#
PCI INTD#
UNASSIGNED
15-1.
# Clocks Past Start
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
96
15-9