Intel 460GX Software Developer’s Manual page 209

11.2.1.8 DBCNT–Dma Base and Current Count Registers (I/O)
I/O Address:
Default Value:
Attribute:
This register determines the number of transfers to be performed. The actual number of transfers is
one more than the number programmed in the Current Byte/Word Count Register When the value
in the register is decremented from zero to FFFFh, a TC is generated. Auto-initialize can only
occur when a TC occurs. If it is not auto-initialized, this register has a count of FFFFh after TC.
For transfers to/from an 8-bit I/O, the Byte/Word count indicates the number of bytes to be
transferred. This applies to DMA channels 0-3. For transfers to/from a 16-bit I/O, with shifted
address, the Byte/Word count indicates the number of 16-bit words to be transferred. This applies
to DMA channels 5-7.
Bit
15:0
11.2.1.9 DLPAGE–DMA Low Page Registers (I/O)
I/O Address:
Default Value:
Attribute:
This register works in conjunction with the Current Address Register. After an auto-initialization,
this register retains the original programmed value. Auto-initialize takes place after a TC.
Bit
7:0
11.2.1.10 DCBP–Dma Clear Byte Pointer Register (I/O)
I/O Address:
Default Value:
Attribute:
Writing to this register executes the Clear Byte Pointer Command. This command is executed prior
to reading/writing a new address or word count to the DMA. The command initializes the byte
pointer flip-flop to a known state so that subsequent accesses to register contents address upper and
lower bytes in the correct sequence. The Clear Byte Pointer Command (or CPURST or the Master
Clear Command) clears the internal latch used to address the upper or lower byte of the 16-bit
Address and Word Count Registers.
Intel® 460GX Chipset Software Developer's Manual
DMA Channel 0–001h
DMA Channel 1–003h
DMA Channel 2–005h
DMA Channel 3–007h
Undefined (CPURST or Master Clear)
Read/Write
Base and Current Byte/ Word Count. These bits represent the 16 byte/word count bits used
when counting down a DMA transfer.
DMA Channel 0–087h
DMA Channel 1–083h
DMA Channel 2–081h
DMA Channel 3–082h
Undefined (CPURST or Master Clear)
Read/Write
DMA Low Page [23:16]. These bits represent address bits [23:16] of the 24-bit DMA address.
Channels 0-3–00Ch; Channels 4-7–0D8h
All bits undefined
Write Only
LPC/FWH Interface Configuration
DMA Channel 4–0C2h
DMA Channel 5–0C6h
DMA Channel 6–0CAh
DMA Channel 7–0CEh
Description
DMA Channel 5–08Bh
DMA Channel 6–089h
DMA Channel 7–08Ah
Description
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