Sdc - Intel 460GX Software Developer’s Manual

2.4.2

SDC

2.4.2.1 SEC0_D_FERR: Data on First Memory Card B SEC
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the data corresponding to the first SEC detected by memory
interface 0 in the SDC.
Bits
63:0
2.4.2.2 SEC0_ECC_FERR: ECC on First Memory Card B SEC
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records and latches the ECC checkbits corresponding to the first SEC detected by
memory interface 0 in the SDC
Bits
7:0
2.4.2.3 SEC0_TXINFO_FERR: TXINFO on First Memory Card B SEC
Bus CBN, Device Number:
Address Offset:
Default Value:
This register records the ITID and failing chunk corresponding to the first SEC detected by
memory interface 0 in the SDC.
Bits
15:9
8:6
5:0
Intel® 460GX Chipset Software Developer's Manual
04h
40-47h
0
Description
DE - System Data of Error.
04h
48h
00h
Description
ECC - ECC of Error.
04h
49-4Ah
00h
Description
reserved(0)
DC - Data Chunk of ITID.
ITID - ITID of error.
Size: 64 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 8 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Size: 16 bits
Attribute: Read Only, New Value Latched
anytime appropriate FERR register
bit is set
Register Descriptions
2-11