Rid-Revision Identification Register (Function 0); Classc-Class Code Register (Function 0); Hedt-Header Type Register (Function 0) - Intel 460GX Software Developer’s Manual

Bit
8
7
6:0
11.1.5 RID–Revision Identification Register (Function 0)
Address Offset:
Default Value:
Attribute:
This 8 bit register contains device stepping information. Writes to this register have no effect.
Bit
7:0
11.1.6 CLASSC–Class Code Register (Function 0)
Address Offset:
Default Value:
Attribute:
This register identifies the Base Class Code, Sub-class Code, and Device Programming interface
for the IFB PCI Function 0.
Bit
23:16
15:8
7:0
11.1.7 HEDT–Header Type Register (Function 0)
Address Offset:
Default Value:
Attribute:
The HEDT Register identifies the IFB as a multi-Function device.
Bit
7:0
Intel® 460GX Chipset Software Developer's Manual
PERR# Response (Not Implemented). Read as 0.
Fast Back to Back–RO. This bit indicates to the PCI Master that IFB as a target is capable of
accepting fast back-to-back transactions. This bit is hardwired to 1.
Reserved.
08h
Stepping Dependent
Read Only
Revision ID Byte.
09h-0Bh
060100h
Read Only
Base Class Code (BASEC). 06h=Bridge device.
Sub-Class Code (SCC). 01h=PCI-to-ISA Bridge. ISA is not supported, IFB forwards cycles to
the LPC interface.
Programming Interface (PI). 00h=No register level programming interface defined.
0Eh
80h
Read Only
Device Type (DEVICET). 80h=multi-Function device.
LPC/FWH Interface Configuration
Description
Description
Description
Description
11-3