Timing Performance; Local Bus To Dram Cycle Times; Rom Cycle Times; Scsi Transfers - Motorola MVME167 Series User Manual

Functional Description
bound cycles. VMEbus bound cycles are timed by the VMEbus access timer and the
VMEbus global timer. Refer to the VMEchip2 in the
MVME166/MVME167/MVME187 Single Board Computers Programmer's Reference
Guide for detailed programming information.

Timing Performance

This section provides the performance information for the MVME167. Various
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MVME167s are designed to operate at 25 MHz or 33 MHz.

Local Bus to DRAM Cycle Times

The PCCchip2 and VMEchip2 have the same local bus interface timing as the
MC68040, therefore the following cycle times also apply to the PCCchip2 and the
VMEchip2. Read accesses to onboard DRAM require 4 bus clock cycles with parity
checking off. With parity checking on and the bus error reported in the current cycle,
5 bus clock cycles are required. Write accesses to onboard DRAM require 2 bus clock
cycles.
Burst read accesses require 7 (4-1-1-1) bus clock cycles with parity check off. With
parity checking on and the bus error reported in the current cycle, 8 (5-1-1-1) bus clock
cycles are required. Burst write cycles require 5 (2-1-1-1) bus clock cycles.
The parity DRAM is organized as four banks; this requires the use of 256K by 4 chips
for the data portion of the RAM and 256K by 4 chips with the write-per-bit option for
the parity bits. The use of four banks allows X-1-1-1 bursts with parity on.

ROM Cycle Times

The ROM cycle time is programmable from 4 to 11 bus clock cycles. The data
transfers are 32 bits wide. Refer to the MVME166/MVME167/MVME187 Single Board
Computers Programmer's Reference Guide.

SCSI Transfers

The MVME167 includes a SCSI mass storage bus interface with DMA controller. The
SCSI DMA controller uses a FIFO buffer to interface the 8-bit SCSI bus to the 32-bit
local bus. The FIFO buffer allows the SCSI DMA controller to efficiently transfer data
to the local bus in four longword bursts. This reduces local bus usage by the SCSI
device.
The first longword transfer of a burst, with snooping disabled, takes four bus clocks
with parity off and five bus clocks with parity on. Each of the remaining three transfers
requires one bus clock.
The transfer rate of the DMA controller is 44 MB/sec at 25 MHz with parity off.
Assuming a continuous transfer rate of 5 MB/sec on the SCSI bus, 12% of the local
bus bandwidth is used by transfers from the SCSI bus.
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