Functional Description; Processor; Pci Host Bridge/Memory Controller; Pci Bus Arbitration - Motorola MVME2100 Installation And Use Manual

Functional Description

Functional Description
3

Processor

PCI Host Bridge/Memory Controller

PCI Bus Arbitration

3-4
This section provides a description of the primary components on the
MVME2100 and in some cases the corresponding functions associated
with those components.
The MVME2100 is designed to support the MPC8240 processor in a 352
pin TBGA package. It is also designed to support memory bus speeds of
50, 60, 66.67, and 83.33 MHz.
The MPC8240 contains an integrated PCI host bridge and memory
controller which provides the bridge function between the internal
MPC60x bus and the external PCI local bus.
The processor supports a 32-bit PCI interface that is compliant with the
PCI Local Bus Specification, Revision 2.1. Additional features of the
processor include:
PReP or CHRP compatible memory maps
DRAM control/refresh
3.3/5.0V compatible I/O
power management support
Boot ROM interface
PCI arbitration for the MVME2100 board is provided by the integrated
PCI arbiter internal to the processor in conjunction with an external sub-
arbiter. The processor provides support for itself and up to five external
PCI masters.
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