Table 3-3. Powerpc 60X Bus To Dram Access Timing When Configured For 50Ns Edo Devices - Motorola MTX Series Programmer's Reference Manual

Falcon ECC Memory Controller Chip Set
Table 3-3. PowerPC 60x Bus to DRAM Access Timing when Configured for
3
ACCESS TYPE
4-Beat Read after Idle (Quad-word
aligned)
4-Beat Read after Idle (Quad-word
misaligned)
4-Beat Read after 4-Beat Read
(Quad-word aligned)
4-Beat Read after 4-Beat Read
(misaligned)
4-Beat Write after Idle
4-Beat Write after 4-Beat Write
(Quad-word aligned)
1-Beat Read after Idle
1-Beat Read after 1-Beat Read
1-Beat Write after Idle
1-Beat Write after 1-Beat Write
3-10
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.
50ns EDO Devices
Notes
1. These numbers assume that the PowerPC 60x bus master is doing
address pipelining with TS_ occurring at the minimum time after
AACK_ is asserted. Also the two numbers shown in 1st beat column
are for page miss/page hit.
2. In some cases, the numbers shown are averages and specific
instances may be longer or shorter.
CLOCK PERIODS REQUIRED FOR:
1st 2nd
Beat Beat
8 1
8 2
1
5/2 1
1
4/2 2
4 1
1
4/3 1
-
8
1
7/5 -
-
4
-
1
9/7
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Total
3rd 4th
Clocks
Beat Beat
1 1
1 1
1 1
1 1
1 1
1 1
- -
- -
- -
- -
11
12
8/5
8/6
7
7/6
8
7/5
4
9/7