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68000 Motherboard User's Manual
parallel groups of bits. If an external asynchronous transition straddles a positive clock
edge, spurious data may result.
Writes to this register are ignored, but the write operation is signaled on the
TP_WRDECRST_6 test point.
Table 15: Clock Synchronization Register Breakdown
Bits
0-2
4-7
7.12. 2.1 On- Board Interrupt Logic Level
Addr: ONBD_BASE+$C0000 (Clock Synchronization Register), bits 0-2
Size: 3 bit
Bits 0-2 of the Clock Synchronization Register report the current interrupt level
recognized by the Interrupt Logic. These three bits represent the output of the on-board
Interrupt Logic that may be connected to the processor's /IPLn pins through the On-
Board Interrupt Logic Enable, A1JP310. It indicates the highest priority level interrupt
event pending. See the Interrupt Logic section for further detail.
7.12. 2.2 The Hardware E ntropy Generator
Addr: ONBD_BASE+$C0000 (Clock Synchronization Register), bit 3
Size: 1 bit
The Hardware Entropy Generator circuit provides a bit whose state is the result of
measuring an avalanche process of a reverse biased diode. This bit appears as bit 3 of the
Clock Synchronization Register.
unpredictable behavior over time and that this can be used as a rudimentary source of
random data for the software application. The avalanche events are accumulated in
hardware by a flip-flop, in order to take advantage of the tally of avalanche events that
occur between software samplings, rather than the instantaneous diode state. This was
done to reduce duty cycle bias of the diode's conducting condition.
With no rigorous development, the typical entropy bandwidth available from the circuit is
estimated as 20k bits/sec in bench testing. Actual performance many vary over a wide
range of factors. But the logic behind this estimate is based on two contributing factors.
The first is the empirically measured average time between bit state transition cycles,
under the interpretation that the state is suitably randomized after this period has elapsed.
Description
On-Board Interrupt Logic Level
3
Hardware Entropy Generator Bit
On-Board Digital Input Interface
The intent is that the avalanche process has an
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Rev. A
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