I/O Port Offset 0Dh: Fpga Register Index Port; Table 4-12. Fpga Register Index Port; Table 4-13. Fpga Register Index - Motorola CPV5000 Installation And Reference Manual

I/O port offset 0Dh: FPGA register index port

A Field Programmable Gate Array (FPGA) on the CPV5000 contains the
watchdog timer and miscellaneous registers. The value written to the index
port selects which FPGA register is accessible from port offset 00Fh. Index-0
is selected at reset and is selected after any output to the FPGA data port offset
0Fh. This last feature helps to protect registers that control important board
operations.
Bit 7 6
Function

Table 4-12. FPGA register index port

5 4
Not used
Table 4-13.
FPGA register index
Index bits 2-0 Index Function
0000 Reserved
0001 Reserved
0010 Reserved
0011 Watchdog index
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 Reserved
1001 Reserved
1010 Reserved
1011 ENUM status/control
1110 ENUM storage
FPGA Access, Watchdog and ENUM registers
3 2 1
FPGA register index
4
0
4-19