Figure 5-2 Shi Clock Generator; Figure 5-3 Shi Programming Model-Host Side - Motorola DSP56009 User Manual

24-bit digital signal processor
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5.2.1
SHI Clock Generator
The SHI clock generator generates the serial clock to the SHI if the interface operates
in the Master mode. The clock generator is disabled if the interface operates in the
Slave mode. When the SHI operates in the Slave mode, the clock is external and is
input to the SHI (HMST = 0). Figure 5-2 illustrates the internal clock path
connections. It is the user's responsibility to select the proper clock rate within the
range as defined in the I
SCK/SCL
Divide
By 2
F
OSC
5.3
SERIAL HOST INTERFACE PROGRAMMING MODEL
The Serial Host Interface programming model is divided in two parts:
• Host side—see Figure 5-3 below and Section 5.3.1 on page 5-8
• DSP side—see Figure 5-4 on page 5-6 and Sections 5.3.2 on page 5-8
through 5.3.6 on page 5-13 for detailed information
23
Figure 5-3 SHI Programming Model—Host Side
MOTOROLA
2
C and SPI bus specifications.
Divide By 1
Divide By
To
1 or 8
Divide By 64
HDM0–HDM5
HRS

Figure 5-2 SHI Clock Generator

IOSR
DSP56009 User's Manual
Serial Host Interface Programming Model
HMST
SHI Clock
HMST = 0
Clock
Logic
HMST = 1
CPHA, CPOL, HI
0
I/O Shift Register (IOSR)
Serial Host Interface
SHI
Controller
2
C
AA0417k
AA0418
5-5

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