Figure 4-10 Host Processor Programming Model-Host Side - Motorola DSP56012 User Manual

24-bit digital signal processor
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Modes
7
INIT
HM1
HM0
$0
(0)
(0)
(0)
0
0
1
1
7
5
HC
$1
0
(0)
7
HOREQ
DMA
$2
(0)
(0)
7
$3
31
$4
0 0 0 0 0 0 0 0
Not Used
7
Note:
1.
The numbers in parentheses are reset initialization values.
Figure 4-10 Host Processor Programming Model–Host Side
MOTOROLA
Flags
HF1
HF0
(0)
(0)
0
Interrupt Mode (DMA Off)
1
24-Bit DMA Mode
0
GPIO-Bit DMA Mode
1
8-Bit DMA Mode
Host Vector
($17)
Flags
HF3
HF2
TRDY
0
(0)
(0)
(1)
Interrupt Vector Number
($0F)
Receive Byte Registers (RXH:RXM:RXL)
(Read Only)
24 23
$5
RXH
Receive High Byte
TXH
Transmit High Byte
0 7
Transmit Byte Registers (TXH:TXM:TXL)
(Write Only)
DSP56012 User's Manual
0
TREQ
RREQ
Interrupt Control Register (ICR)
0
(Read/Write)
(1)
(0)
0
Command Vector Register (CVR)
(Read/Write)
Status
0
TXDE
RXDF
Interrupt Status Register (ISR)
(Read Only)
(1)
(0)
0
Interrupt Vector Register (IVR)
(Read/Write)
16 15
$6
RXM
Receive Middle Byte
TXM
Transmit Middle Byte
0 7
Parallel Host Interface
Host Interface (HI)
8 7
$7
RXL
Receive Low Byte
TXL
Transmit Low Byte
0 7
AA0319k
4-23
0
0

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