Omron SYSMAC CJ Series User Manual page 152

7 High-speed Counters
Name
High-speed
Counter 0 Gate Bit
High-speed
Counter 1 Gate Bit
High-speed
Counter 2 Gate Bit
High-speed
Counter 3 Gate Bit
7-42
Word/Bit Function
A531.08 If one of these flags is turned ON,
the high-speed counter will not
count even if pulse inputs are
received and the counter PV will be
A531.09
maintained at its current value.
When the flag is turned OFF, the
high-speed counter will resume
A531.10
counting and the counter PV will be
refreshed.
This flag will be disabled if the high-
speed counter's reset method is set
A531.11
to Phase-Z signal + Software reset
and the Reset Bit (A531.00 to
A531.03) is ON.
Read/Write Refresh timing
Read/Write • Cleared when power is
turned ON.
CJ2M CPU Unit Pulse I/O Module User's Manual