Omron SYSMAC CJ Series User Manual page 151

Name
High-speed
Counter 3 Count
Direction
High-speed
Counter 0 Range
Comparison Con-
dition 1 to 32 In-
range Flags
High-speed
Counter 1 Range
Comparison Con-
dition 1 to 32 In-
range Flags
High-speed
Counter 2 Range
Comparison Con-
dition 1 to 32 In-
range Flags
High-speed
Counter 3 Range
Comparison Con-
dition 1 to 32 In-
range Flags
High-speed
Counter 0 Ring
Counter Maximum
Value
High-speed
Counter 1 Ring
Counter Maximum
Value
High-speed
Counter 2 Ring
Counter Maximum
Value
High-speed
Counter 3 Ring
Counter Maximum
Value
High-speed
Counter 0 Reset
Bit
High-speed
Counter 1 Reset
Bit
High-speed
Counter 2 Reset
Bit
High-speed
Counter 3 Reset
Bit
CJ2M CPU Unit Pulse I/O Module User's Manual
Word/Bit Function
A321.10 This flag indicates whether high-
speed counter 3 is currently being
incremented or decremented. The
counter PV for the current cycle is
compared with the PV in last cycle
to determine the result.
OFF: Decrementing
ON: Incrementing
A10128 and These flags indicate whether the
A10129 PV is within any of the 1 to 32
ranges when a high-speed counter
(0 to 3) is being operated in range-
comparison mode with upper and
lower limits.
A10130 and
A10131
The In-range Flags, however, will be
ON whenever the comparison value
is within the range regardless of the
whether the high-speed counter is
set to execute the interrupt task
A10132 and
when the range is entered or left.
A10133
OFF: Not in range
ON: In range
Bits 00 to 15 in the lower word cor-
A10134 and
respond to ranges 1 to 16. Bits 00
A10135
to 15 in the upper word correspond
to ranges 17 to 32.
A10136 and Contain the ring counter maximum
A10137 values when high-speed counters 0
to 3 are used as ring counters.
These values are cleared to 0 if Lin-
A10138 and
ear Mode is used.
A10139
Lower four digits: A10136, A10138,
A10140, and A10142
Upper four digits: A10137, A10139,
A10140 and
A10141, and A10143
A10141
A10142 and
A10143
A531.00 When the reset method is set to a
phase-Z signal + software reset, the
corresponding high-speed counter's
PV will be reset if the phase-Z sig-
A531.01
nal is received while this flag is ON.
When the reset method is set to a
software reset, the corresponding
A531.02
high-speed counter's PV will be
reset in the cycle when this bit turns
ON.
A531.03
7 High-speed Counters
Read/Write Refresh timing
Read • Setting used for high-
speed counter, valid
during counter opera-
tion.
Read • Cleared when power is
turned ON.
• Cleared when opera-
tion is started.
• Refreshed each cycle
(overseeing process-
ing).
• Refreshed when com-
parison is executed for 1
to 32 ranges.
• Refreshed when
PRV(881) instruction is
executed to read the
results of range compar-
ison.
• Refreshed when
INI(880) instruction is
executed to change PV
or ring counter maxi-
mum value.
• Reset
Read • Cleared when power is
turned ON.
• Cleared when opera-
tion starts.
• Refreshed when
INI(880) instruction is
executed to change ring
counter maximum
value.
Read/Write • Cleared when power is
turned ON.
7
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