Power On Sequence Test
When the disk array is powered on, it goes through a power on sequence test, during which time various
numbers are displayed on the front panel. The numbers step higher as each initialization step is completed.
The changing sequence numbers assure you that the disk array is performing the various power-on tests.
When the tests have all completed, the front panel will display the word "ready." If the word "ready" is not
eventually displayed, the sequence number at which the power on stops will help diagnose what might have
went wrong.
Sequence
Code
Description of Power On Sequence Test Performed
1
host SRAM test; parity SRAM test
4
chip register test; data path tests
6
ROM test; copy perf code to SRAM
10
delay for mirror to come up; start mirrored communications
12
check backplane
16
start early spinup
20
local NVRAM pretest
22
remote NVRAM pretest
24
local NVRAM decode test
26
setup remote NVRAM decode test
28
remote NVRAM decode test
30
SIMM 1, 1st half test
32
SIMM 1, 2nd half test (32 MB SIMMs only)
34
SIMM 2, 1st half test
36
SIMM 2, 2nd half test (32 MB SIMMs only)
38
remote SIMM 1, 1st half test
40
remote SIMM 1, 2nd half test (32 MB SIMMs only)
42
remote SIMM 2, 1st half test
Table 9. Power On Sequence Test
Troubleshooting
Power On Sequence Test
121