Tsb Organization; Tsb Pointer Formation - Fujitsu SPARC JPS1 Implementation Supplement Manual

F.3.3

TSB Organization

IMPL. DEP. #227
dependent in JPS1. See impl. dep. #228 for the limitation of TSB_size in TSB
registers.
SPARC64 V supports a maximum of 16 million lines in the common TSB and a
maximum 32 million lines in the split TSB. The maximum number N in
FIGURE
F.4.2

TSB Pointer Formation

IMPL. DEP. #228
from a context-ID register is implementation dependent in JPS1. Only for cases of
direct hash with context-ID can the width of the TSB_size field be wider than 3
bits.
On SPARC64 V, TSB_Hash is supplied from a context-ID register. The width of
the TSB_size field is 4 bits.
IMPL. DEP. #229
exclusive-ORing the TSB Base Register and a TSB Extension Register or by taking the
TSB_Base field directly from the TSB Extension Register is implementation
dependent in JPS1. This implementation dependency is only to maintain
compatibility with the TLB miss handling software of UltraSPARC I/II.
On SPARC64 V, when ASI_MCNTL.JPS1_TSBP = 1, the TSB Base address is
generated by taking TSB_Base field directly from the TSB Extension Register.
TSB Pointer Formation
On SPARC64 V, the number N in the following equations ranges from 0 to 15; N is
defined to be the TSB_Size field of the TSB Base or TSB Extension Register.
SPARC64 V supports the TSB Base from TSB Extension Registers as follows when
ASI_MCNTL.JPS1_TSBP = 1.
For a shared TSB (TSB Register split field = 0):
8K_POINTER = TSB_Extension[63:13+N]
0000
64K_POINTER = TSB_Extension[63:13+N]
0000
For a split TSB (TSB Register split field = 1):
88 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
: The maximum number of entries in a TSB is implementation
F-4 of Commonality
is
: Whether TSB_Hash is supplied from a TSB Extension Register or
: Whether the implementation generates the TSB Base address by
20
16 million (16 * 2 ).
(VA[21+N:13]
(VA[24+N:16]
TSB_Hash)
TSB_Hash)