Fujitsu SPARC JPS1 Implementation Supplement Manual page 195

Column Term
Error Detect Always
Condition
always
AUG
LDXA
LDXA #I
LDXA #D
ITLB write
DTLB write
Use for TLB
Enabled
intr_receive Error is checked when the UPA interrupt packet is received. When an
BV interface
184 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Meaning
Error is always checked.
Error is checked when (ASI_ERROR_CONTROL.UGE_HANDLER = 0) &&
(ASI_ERROR_CONTROL.WEAK_ED = 0).
Error is checked when the register is read by LDXA instruction.
Error is checked when the register is read by LDXA instruction.
Also, the register is used for the calculation of IMMU_TSB_8KB_PTR and
IMMU_TSB_64KB_PTR. When the register has a
for the calculation of ASI_IMMU_TSB_PTR registers, the
the ASI_IMMU_TSB_PTR registers. Upon execution of the LDXA instruction
to read ASI_IMMU_TSB_PTR with the propagated
detected.
Error is checked when the register is read by LDXA instruction.
Also, the register is used for the calculation of DMMU_TSB_8KB_PTR,
DMMU_TSB_64KB_PTR, and DMMU_TSB_DIRECT_PTR. When the register has
a and the register is used for the calculation of ASI_DMMU_TSB_PTR
UE
registers, the is propagated to the ASI_DMMU_TSB_PTR registers. Upon
UE
execution of the LDXA instruction to read ASI_DMMU_TSB_PTR with the
propagated , the
IUG_TSBP
UE
Error is checked at the ITLB update timing after completion of the STXA
instruction to write or demap an ITLB entry.
Error is checked at the DTLB update timing after the completion of the STXA
instruction to write or demap a DTLB entry.
Error is checked when the register is used for a TLB reference.
Error is checked when the facility is enabled.
uncorrectable error is detected in the received interrupt packet, the vector
interrupt trap is caused but ASI_INTR_RECEIVE.BUSY = 0 is set. In this
case, a new interrupt packet can be received after software writes
ASI_INTR_RECEIVE.BUSY = 0.
Uncorrected error in the Barrier Variable transfer interface between the
processor and the memory system is checked during the AUG_always
period.
and the register is used
UE
, the
UE
error is detected.
(2 of 3)
is propagated to
UE
error is
IUG_TSBP