Fujitsu SPARC JPS1 Implementation Supplement Manual page 16

Extended UPA Bus
SX-Unit
UPA interface logic
MoveIn buffer
U2$
tag
S-Unit interface
S-Unit
SX interface
I-TLB tag
2048
Level-1 I cache
+ 32
128 KB, 2-way
entry
I-Unit
Instruction Instruction
fetch buffer
pipeline
Branch
history
SPARC64 V Major Units
FIGURE 1-1
Release 1.0, 1 July 2002
MoveOut buffer
U2$ data
2M 4-way
SX order queue Store queue
data
D-TLB tag
2048
Level-1 D cache
+ 32
128 KB, 2-way
entry
Commit stack entry
Reservation stations
E-Unit
ALU
Input
Registers
and
Output
Registers
data
PC
nPC
CCR
FSR
ALUs
EXA
EXB
FLA
FLB
EAGA
EAGB
GUB FUB
GPR FPR
E-unit
control
logic
F. Chapter 1 Overview 5