Level-2 Cache Control Register (Asi_L2_Ctrl); L2 Diagnostics Tag Read (Asi_L2_Diag_Tag_Read) - Fujitsu SPARC JPS1 Implementation Supplement Manual

M.3.2

Level-2 Cache Control Register (ASI_L2_CTRL)

[1]
[2]
[3]
[4]
[5]
ASI_L2_CTRL
It is illustrated below and described in
URGENT_ERROR_TRAP
Reserved
63 25
ASI_L2_CTRL
TABLE M-6
Bit Field
24
URGENT_ERROR_TRAP
18:16
NUMINSWAY
0
U2_FLUSH
M.3.3 L2 Diagnostics Tag Read
(ASI_L2_DIAG_TAG_READ)
This ASI instruction is a diagnostic read of L2 cache tag, as well as tag 2 of L1I and
L1D.
130 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Register Name:
ASI:
VA:
RW
Data
is a control register for L2 training, interface, and size configuration.
Reserved
24 23
Register Bits
RW Description
RW1C This bit is set to 1 when one of the error exceptions
(
instruction_access_error
exception is generated. The bit remains set to 1 until supervisor
software explicitly clears it by writing 1 to the bit.
R Set associativity of L2 cache, as follows:
W Flush the entire level-2 cache. The flushing takes approximately 10
ms, Until the flushing of the level-2 cache completes, the processor
ceases operation and does not perform further instruction
execution.
ASI_L2_CTRL
6A
16
10
16
Supervisor read/write
.
TABLE M-6
NUMINSWAY
19 18
,
data_access_error
2
4:
U2_FLUSH
Reserved
16 15 1
, or
asynchronous_data_error
2-way mode
4-way mode
0
)