Table of Contents
Advertisement
8K_POINTER = TSB_Extension[63:14+N]
64K_POINTER = TSB_Extension[63:14+N]
TSB_Hash)
Value of TSB_Hash for both a shared TSB and a split TSB
When 0 <= N <= 4,
Otherwise, when 5 <= N <= 15,
F.5
Faults and Traps
IMPL. DEP. #230
dependent in JPS1, but there are several mandatory causes of
trap.
SPARC64 V signals a
Commonality. However, caution is needed to deal with an invalid ASI. See
Section F.10.9 for details.
IMPL. DEP. #237
captured when
instruction is implementation dependent.
On SPARC64 V, the fault status and address (DSFSR/DSFAR) are not captured
when a
instruction.
Additional information: On SPARC64 V, the two precise traps—
instruction_access_error
to those in
that table is shown below.
MMU Trap Types, Causes, and Stored State Register Update Policy
TABLE F-2
Ref #Trap Name
1.
fast_instruction_access_MMU_miss
Release 1.0, 1 July 2002
0000
0000
TSB_Hash = context_register[N+8:0]
TSB_Hash[ 12:0 ] = context_register[ 12:0 ]
TSB_Hash[ N+8:13 ] = 0 ( N-4 bits zero )
: The cause of a
data_access_exception
: Whether the fault status and/or address (DSFSR/DSFAR) are
mem_address_not_aligned
mem_address_not_aligned
and
F-2 of Commonality. A modification (the two traps are added) of
TABLE
Trap Cause
I-TLB miss
data_access_exception
for the causes, as defined in F.5 in
is generated during a JMPL or RETURN
exception is generated during a JMPL or RETURN
—are recorded by the MMU in addition
data_access_error
I-SFSR
X2
F. Chapter F
0
(VA[21+N:13]
1
(VA[24+N:16]
trap is implementation
data_access_exception
Registers Updated
(Stored State in MMU)
I-MMU
D-MMU
Tag
D-SFSR,
Tag
Access
SFAR
Access Trap Type
X
Memory Management Unit
TSB_Hash)
64
–67
16
16
89
Advertisement
Table of Contents
