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detects any conditions for an
Subtract instruction generates the
cexc, or aexc are modified.
Exceptions in Floating-Point Multiply-Add/Subtract Instructions
TABLE A-2
IEEE754 trap
FMUL
—
FADD/SUB
cexc
Exception condition of FMUL Exception condition of FADD
aexc
No change
Detailed contents of cexc and aexc depending on the various conditions are
described in
and nx are nontrapping IEEE exception conditions—underflow, overflow, invalid
operation, and inexact, respectively.
TABLE A-3
FMUL
TABLE A-4
FMUL
In the tables, the conditions in the shaded columns are all reported as an
unfinished_FPop
exist.
52
SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
No trap
IEEE754 trap
No change
and
TABLE A-3
Non-Trapping cexc When
none
none
none
nx
nx
of nx
of nx
uf nx
uf nx
inv
inv
Non-Trapping aexc When
none
none
none
nx
nx
of nx
of nx
uf nx
uf nx
inv
inv
trap by SPARC64 V. In addition, the conditions with "
trap, the Floating-point Multiply-Add/
unfinished_FPop
unfinished_FPop
. The following terminology is used: uf, of, inv,
TABLE A-4
= 0
FSR.NS
FADD
nx
of nx
nx
of nx
nx
of nx
of nx
of nx
uf nx
uf of nx
—
—
= 1
FSR.NS
FADD
nx
of nx
uf nx
nx
of nx
uf nx
nx
of nx
uf nx
of nx
of nx
—
—
—
—
—
—
—
exception. In this case, none of rd,
No trap
No trap
Logical or of the nontrapping exception
conditions of FMUL and FADD/SUB
Logical OR of the cexc (above) and the
aexc
inv
inv
inv nx
inv of nx
uf inv nx
inv
inv
inv
inv nx
inv of nx
uf inv nx
inv
—
" do not
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