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TABLE C-1
Nbr
218
219
220
221
222
223
224
225
226
Release 1.0, 1 July 2002
SPARC64 V Implementation Dependencies (8 of 11)
SPARC64 V Implementation Notes
async_data_error
trap is implemented in
async_data_error
Appendix P for details.
Asynchronous Fault Address Register (
SPARC64 V
implements two AFARs:
• VA = 00
for an error occurring in D1 cache.
16
• VA = 08
for an error occurring in U2 cache.
16
Addition of logging and control registers for error handling
SPARC64 V
implements various features for sustaining reliability. See
Appendix P for details.
Special/signalling ECCs
The method to generate "special" or "signalling" ECCs and whether
processor-ID is embedded into the data associated with special/signalling
ECCs is implementation dependent.
TLB organization
SPARC64 V has the following TLB organization:
• Level-2 micro ITLB (uITLB), 32-way fully associative
• Level-1 micro DTLB (uDTLB), 32-way fully associative
• Level-2 IMMU-TLB—consisting of sITLB (set-associative Instruction TLB)
and fITLB (fully associative Instruction TLB).
• Level-2 DMMU-TLB—consisting of sDTLB (set-associative Data TLB) and
fDTLB (fully associative Data TLB).
TLB multiple-hit detection
On SPARC64 V, TLB multiple hit detection is supported. However, the
multiple hit is not detected at every TLB reference. When the micro-TLB
(uTLB), which is the cache of sTLB and fTLB, matches the virtual address,
the multiple hit in sTLB and fTLB is not detected. The multiple hit is
detected only when the micro-TLB mismatches and the main TLB is
referenced.
MMU physical address width
The SPARC64 V MMU implements 43-bit physical addresses. The PA field of
the
TTE
holds a 43-bit physical address. Bits 46:43 of each TTE always read
as 0 and writes to them are ignored. The MMU translates virtual addresses
into 43-bit physical addresses. Each cache tag holds bits 42:6 of physical
addresses.
TLB locking of entries
In SPARC64 V, when a TTE with its lock bit set is written into TLB through
the Data In register, the TTE is automatically written into the corresponding
fully associative TLB and locked in the TLB. Otherwise, the TTE is written
into the corresponding sTLB of fTLB, depending on its page size.
TTE support for CV bit
SPARC64 V
does not support the CV bit in TTE. Since I1 and D1 are
virtually indexed caches, unaliasing is supported by
impl. dep. #232.
SPARC64 V
, using tt = 40
AFAR
) allocation
SPARC64 V
F. Chapter C
Implementation Dependencies
Page
39
. See
16
177, 178
—
—
85
86
86
87
87
. See also
77
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